计算机测量与控制
計算機測量與控製
계산궤측량여공제
COMPUTER MEASUREMENT & CONTROL
2010年
3期
562-564
,共3页
SRAM单元%亚阈值漏电流%低功耗%数据Cache
SRAM單元%亞閾值漏電流%低功耗%數據Cache
SRAM단원%아역치루전류%저공모%수거Cache
SRAM cell%subthreshold leakage%low power%data Cache
随着工艺尺寸及处理器频率的提高,Cache的功耗已经成为处理器功耗的重要来源,数据Cache的亚阈值漏电流功耗在总功耗中的比重也在上升;提出一种通过降低未被访问的Cache line的亚阈值漏电流功耗来降低整个数据Cache功耗的控制策略;该策略对所有Cache line周期性地提供低电压,从而降低了SRAM单元的亚阈值漏电流;当某一行被访问时,提供正常的电压,直到下一次被周期性地控制提供低电压;仿真结果显示,此策略以较少的硬件代价和访问延迟显著地降低了数据Cache的亚阈值漏电流功耗.
隨著工藝呎吋及處理器頻率的提高,Cache的功耗已經成為處理器功耗的重要來源,數據Cache的亞閾值漏電流功耗在總功耗中的比重也在上升;提齣一種通過降低未被訪問的Cache line的亞閾值漏電流功耗來降低整箇數據Cache功耗的控製策略;該策略對所有Cache line週期性地提供低電壓,從而降低瞭SRAM單元的亞閾值漏電流;噹某一行被訪問時,提供正常的電壓,直到下一次被週期性地控製提供低電壓;倣真結果顯示,此策略以較少的硬件代價和訪問延遲顯著地降低瞭數據Cache的亞閾值漏電流功耗.
수착공예척촌급처리기빈솔적제고,Cache적공모이경성위처리기공모적중요래원,수거Cache적아역치루전류공모재총공모중적비중야재상승;제출일충통과강저미피방문적Cache line적아역치루전류공모래강저정개수거Cache공모적공제책략;해책략대소유Cache line주기성지제공저전압,종이강저료SRAM단원적아역치루전류;당모일행피방문시,제공정상적전압,직도하일차피주기성지공제제공저전압;방진결과현시,차책략이교소적경건대개화방문연지현저지강저료수거Cache적아역치루전류공모.
As feature size shrinks and the frequency increases, on-chip caches represent a sizable fraction of the total power consump-tion of microprocessors. Additionally, subthreshold leakage current as a percentage of total power consumption is on the rise. This paper presents a controlling policy that reduces the total Cache power by reducing the subthreshold leakage power of the Cache lines that are not accessed. It provides lower voltage to all the Cache lines periodically to reduce the subthreshold leakage current in SRAM ceils. Normal voltage will be supplied to a line when it is accessed until the next cyclic lowvoltage signal arrives. The simulation results show that it can reduce the subthreshold leakage power of the data Cache effcidently at the expense of a little additional hardware and a slight performance loss.
