CAJ | 학술논문

提出了一个用于CMOS图像传感器的9位10MS/s、低功耗流水线ADC.为降低功耗,该设计通过采用低功耗、宽摆幅的带有增益增强结构的放大器以及将所有单元共用偏置电路的技术来实现.共用偏置技术需要仔细的版图设计和在电路中加入大的去耦合电容来实现.此外,设计中也采用电容阵列DAC来降低功耗.同时,为了增大信号处理范围,设计中还采用低阈值电压的MOS管.该ADC采用4M-1P的0.18μm CMOS工艺设计制造.对芯片的测试结果表明该设计的功耗仅为7mW,相对其他设计是相当低的.该ADC已经应用于30万像素图像传感器系统中,该系统已经流片、测试.
제출료일개용우CMOS도상전감기적9위10MS/s、저공모류수선ADC.위강저공모,해설계통과채용저공모、관파폭적대유증익증강결구적방대기이급장소유단원공용편치전로적기술래실현.공용편치기술수요자세적판도설계화재전로중가입대적거우합전용래실현.차외,설계중야채용전용진렬DAC래강저공모.동시,위료증대신호처리범위,설계중환채용저역치전압적MOS관.해ADC채용4M-1P적0.18μm CMOS공예설계제조.대심편적측시결과표명해설계적공모부위7mW,상대기타설계시상당저적.해ADC이경응용우30만상소도상전감기계통중,해계통이경류편、측시.
A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed.In the design,the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure,and biasing all the cells with the same voltage bias source,which requires careful layout design and large capacitors.In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range.The ADC was implemented in a 0.18μm 4M-1P CMOS process,and the experimental results indicate that it consumes only 7mW,which is much less than general pipeline ADCs.The ADC was used in a 300000 pixels CMOS image sensor.