CAJ | 학술논문

采样保持电路的信号精度和建立速度直接影响到整个流水线型模数转换器的分辨率和转换速率.本文改进了辅助运放的共模反馈结构,解决了传统结构中跨导运放连续时间共模反馈(CMFB)电路设计困难,偏置电路复杂的问题,使用工作在饱和区边沿的MOS管对实现反馈结构,使输出共模电平在1.65 v快速稳定.该采样保持电路基于0.5 μm 2P3M CMOS工艺,使ADC达到了10位,40 MHz的性能,一级采样电路在3.3 V的电压下其功耗为6 mW.
채양보지전로적신호정도화건립속도직접영향도정개류수선형모수전환기적분변솔화전환속솔.본문개진료보조운방적공모반궤결구,해결료전통결구중과도운방련속시간공모반궤(CMFB)전로설계곤난,편치전로복잡적문제,사용공작재포화구변연적MOS관대실현반궤결구,사수출공모전평재1.65 v쾌속은정.해채양보지전로기우0.5 μm 2P3M CMOS공예,사ADC체도료10위,40 MHz적성능,일급채양전로재3.3 V적전압하기공모위6 mW.
Sample-and-hold circuit is in the front of the ADC, the setting error circuit, which affects the resolution and speed of the whole pipelined ADC directly. To conquer the difficulty of designing in the tradition OTA of CMFB and to debase the complexity in the biasing circuit, we ameliorate the configuration of CMFB of assistant operational amplifier, and use a pair of MOS, which works in the edge of saturation area to form the configuration of feedback. The common-mode voltage is 1.65 V that electrical level is fast and pipelined ADC is researched and designed. The ADC which based on this is 6mW when the fist sample circuit is under the press of 3.3 V.