CAJ | 학술논문

采用TSMC 0.18 μm CMOS 工艺实现了一个20 Gbit/s 1∶2分接器,分接器由主从从、主从D触发器和数据输出缓冲组成.D触发器单元采用动态负载结构,其偏置晶体管采用单时钟输入的共栅结构.动态负载结构的触发器工作速度更快因为它减小了输出点的冲放电时间,而且由于工作时电流处于开关模式,其功耗更低.另外,触发器中采用交叉耦合的正反馈三极管对,加快了整个电路的速度.通过在片晶圆测试,该芯片在输入20 Gbit/s、长度为223-1的伪随机码时工作良好.功耗仅为108 mW,芯片面积为475 μm×578 μm.
채용TSMC 0.18 μm CMOS 공예실현료일개20 Gbit/s 1∶2분접기,분접기유주종종、주종D촉발기화수거수출완충조성.D촉발기단원채용동태부재결구,기편치정체관채용단시종수입적공책결구.동태부재결구적촉발기공작속도경쾌인위타감소료수출점적충방전시간,이차유우공작시전류처우개관모식,기공모경저.령외,촉발기중채용교차우합적정반궤삼겁관대,가쾌료정개전로적속도.통과재편정원측시,해심편재수입20 Gbit/s、장도위223-1적위수궤마시공작량호.공모부위108 mW,심편면적위475 μm×578 μm.
A 1∶2 demultiplexer(DEMUX) that is fabricated using 0.18 μm CMOS (complementary metal-oxide-semiconductor transistor) technology is presented.The DEMUX consists of a master-slave-slave,master-slave D flip-flops and output buffers.The D flip-flop employs a dynamic-loading structure and common-gate topology with single clock phase for the bias transistors.The dynamic-loading structure can make the circuit work faster because it decreases the charge/discharge time of the output node, and it consumes lower power because its working current is in a switch mode.In addition,the positive feedback loop, which is made up of a cross-coupled transistor pair in the latch, speeds up the circuit.Measurement results at 20 Gbit/s 223-1 pseudo random bit sequence (PRBS) via on-wafer testing show that the 1∶2 DEMUX can operate well.The power dissipation is 108 mW with the area of 475 μm×578 μm.