CAJ | 학술논문

针对自动时钟树综合和时钟网格＋局部树这两种设计方法的优缺点，提出了一种结合两钟方式的改进的时钟设计方案一时钟网格＋局部树自动综合（MLTAS），并将该方案应用于北斗二代用户系统的一款SOC芯片的设计中。在相同设计条件下，通过将该设计方案与自动综合的树形结构加以比较，结果显示：MLTAS比CTS可以实现更小的时钟偏差，同时可以降低缓冲器的数量。所以在高性能芯片设计中MLTAS比CTS更适合在时钟网络中的设计。
침대자동시종수종합화시종망격＋국부수저량충설계방법적우결점，제출료일충결합량종방식적개진적시종설계방안일시종망격＋국부수자동종합（MLTAS），병장해방안응용우북두이대용호계통적일관SOC심편적설계중。재상동설계조건하，통과장해설계방안여자동종합적수형결구가이비교，결과현시：MLTAS비CTS가이실현경소적시종편차，동시가이강저완충기적수량。소이재고성능심편설계중MLTAS비CTS경괄합재시종망락중적설계。
According to the advantages and disadvantages of two design methods which are ClockMesh and ClockTree Synthesize, a improved design method that is constitute by them is proposed in this artical, which combine ClockMesh and LocalTree Auto Synthesize （MLTAS）. This method is implemented on a SOC chip which is used in the users＇ system of BD-2. Under the same conditions, compared results of MLTAS and auto synthesized tree structure, and it shows that the MLTAS is able to achieve smaller clock skew and fewer buffers than the auto synthesied methord, so MLTAS is more suitable for the high performance chip design than CTS in the clock network design.