CAJ | 학술논문

高级综合结果中常量元件和输出悬空端口导致门级工艺映射结果中存在显式冗余.显式冗余无助于提高电路性能，反而增加功耗，降低电路的可测试性，使电路面积增大，应予消除.文中提出了显式冗余的队列循环优化算法，完全消除了此类冗余，从而有效地减少了生成电路的基片面积，提高了电路的可测试性.
고급종합결과중상량원건화수출현공단구도치문급공예영사결과중존재현식용여.현식용여무조우제고전로성능，반이증가공모，강저전로적가측시성，사전로면적증대，응여소제.문중제출료현식용여적대렬순배우화산법，완전소제료차류용여，종이유효지감소료생성전로적기편면적，제고료전로적가측시성.
Constant components and output opened ports in the result of high-level synthesis lead to explicit redundancy in gate-level technology mapping.Explicit redundancy can not improve the performance,but increases power consumption,enlarges circuit area and decreases its testability,so it should be removed.This paper proposes a queue loop optimization algorithm to remove explicit redundancy completely which decreases the circuit area and improves the testability.