CAJ | 학술논문

针对差分式电容传感器,提出了一种结构简单的低噪声、低失调电容读出电路.该电路由2相非交叠时钟控制,且对电路的寄生电容不敏感,可直接将传感器电容的变化量转化为电压信号输出.相关双采样(CDS,correlated double sampling)技术有效降低了电路的低频噪声和失调电压的影响,提高了读出电路的分辨率和动态范围.读出电路在0.35μm 2P4M标准CMOS工艺下设计流片,芯片面积为0.7mm×1.8mm,5V电源电压.电路工作在1MHz的时钟频率下,实现了0.4aF/√Hz的电容分辨率和118dB的动态范围.
침대차분식전용전감기,제출료일충결구간단적저조성、저실조전용독출전로.해전로유2상비교첩시종공제,차대전로적기생전용불민감,가직접장전감기전용적변화량전화위전압신호수출.상관쌍채양(CDS,correlated double sampling)기술유효강저료전로적저빈조성화실조전압적영향,제고료독출전로적분변솔화동태범위.독출전로재0.35μm 2P4M표준CMOS공예하설계류편,심편면적위0.7mm×1.8mm,5V전원전압.전로공작재1MHz적시종빈솔하,실현료0.4aF/√Hz적전용분변솔화118dB적동태범위.
This paper presents a novel structure of capacitive readout circuit for fully differential capacitive sensor. The operation of this circuit is controlled by a nonoverlapping two-phase clock. This circuit is not sensitive to parasitic capacitor. Using correlated double sampling(CDS) , the low-frequency noise and voltage offset have been suppressed, so that the resolution and dynamic range of the circuit have been improved. The experiment chip has been fabricated in the standard 0.35μm CMOS process, with a single 5V power supply, and the die size is 0.7mm × 1.8mm. The results show that the readout circuit achieves a resolution of 0.4aF/√ Hz with 118dB dynamic range under 1MHz sampling frequency.