CAJ | 학술논문

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mm P/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mm P/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,
수착대규모화초대규모집성전로특정척촌향아미미、심아미미발전,하일대집성전로대규편적표면정체완정성화전학성능제출료경고적요구.여함유고밀도정체원생결함적규포광편상비,규외연편일반능만족저사요구.해문보도료응용우선진집성전로적150mm P/P+CMOS규외연편연구진전.재PE2061규외연로상진행료P/P+규외연생장.외연편특정삼수,여외연층후도、전조솔균균성,과도구관도급소자산생수명진행료상세표정.연구표명:150mm P/P+CMOS규외연편능구만족선진집성전로대재료경고요구,
With the device feature's size miniaturization in very large scale integrated circuit and ultralarge scale integrated circuit towards the sub-micron and beyond level, the next generation of IC device requires silicon wafers with more improved electrical characteristics and reliability as well as a high perfection of the wafer surface. Compared with the polished wafer with a relatively high density of crystal originated defects (e. g. COPs), silicon epi-wafers can meet such high requirements. The current development of researches on the 150mm-silicon epi-wafers for advanced IC applications is described. The P/P+ CMOS silicon epi-wafers were fabricated on a PE2061 Epitaxial Reactor (made by Italian LPE Company). The material parameters of epiwafers, such as epi-defects, uniformity of thickness and resistivity, transition width, and minority carrier generation lifetime for epi-layer were characterized in detail. It is demonstrated that the 150mm silicon epi-wafers on PE2061 can meet the stringent requirements for the advanced IC applications.