CAJ | 학술논문

利用CMOS晶体管迁移率和阈值电压温度效应相互补偿的原理,采用CSMC-HJ 0.6μm CMOS技术设计了一种稳定的带隙参考电压源,该带隙参考电压源可以在0～85℃、电源电压 4.5～5.5V的范围内正常工作,输出参考电压为1.122～1.176V, 输出参考电压浮动比例小于±3.70%. 包括键合用的焊盘在内,芯片的总面积仅为0.4 mm×0.4 mm,当电源电压在4.5～5.5V范围内变化时,电路总的功率消耗在28.3～48.8 mW 之间浮动.
이용CMOS정체관천이솔화역치전압온도효응상호보상적원리,채용CSMC-HJ 0.6μm CMOS기술설계료일충은정적대극삼고전압원,해대극삼고전압원가이재0～85℃、전원전압 4.5～5.5V적범위내정상공작,수출삼고전압위1.122～1.176V, 수출삼고전압부동비례소우±3.70%. 포괄건합용적한반재내,심편적총면적부위0.4 mm×0.4 mm,당전원전압재4.5～5.5V범위내변화시,전로총적공솔소모재28.3～48.8 mW 지간부동.
On the basis of mutual compensation of mobility and threshold voltage temperature effects, a stable CMOS band-gap voltage reference circuit was designed and fabricated in CSMC-HJ 0.6 μm CMOS technology. Operating from 0 to 85 ℃ under a supply voltage ranging from 4.5 to 5.5 V, the voltage reference circuit offers an output reference voltage ranging from 1.122 to 1.176 V and a voltage variation less than ±3.70%. The chip size including bonding pads is only 0.4 mm×0.4 mm and the power dissipation falls inside the scope of 28.3 to 48.8 mW operating at a supply voltage of 4.5 to 5.5 V.