CAJ | 학술논문

摘要：为了实现高速锁相环电路，通过分析经典CMOS锁相环的鉴相鉴频器，针对其延迟时间过长的问题，设计了可用于CMOS锁相环中的快速鉴相鉴频器．整个电路采用了0．13μmCMOS工艺，通过HSpice仿真软件测试表明，该快速鉴相鉴频器与经典鉴相鉴频器相比，延迟时间可以缩短一半．
적요：위료실현고속쇄상배전로，통과분석경전CMOS쇄상배적감상감빈기，침대기연지시간과장적문제，설계료가용우CMOS쇄상배중적쾌속감상감빈기．정개전로채용료0．13μmCMOS공예，통과HSpice방진연건측시표명，해쾌속감상감빈기여경전감상감빈기상비，연지시간가이축단일반．
To implement high speed phase-locked loops circuit, on the basis of analyzing the conventional phase/frequency detector of CMOS phase-locked loops, a fast phase/frequency detector is designed for the CMOS phase-locked loops to reduce the delay time. The circuit is designed by using the 0. 13 μm CMOS process and HSpice simulating results show that the designed fast phase/frequency detector can reduce half de- lay time.