微电子学
微電子學
미전자학
MICROELECTRONICS
2010年
2期
173-176
,共4页
吴倩瑜%张正璠%李儒章%石立春
吳倩瑜%張正璠%李儒章%石立春
오천유%장정번%리유장%석립춘
A/D转换器%数字抽取滤波器%标准符号编码%级联梳状滤波器
A/D轉換器%數字抽取濾波器%標準符號編碼%級聯梳狀濾波器
A/D전환기%수자추취려파기%표준부호편마%급련소상려파기
A/D converter%Digital decimation filter%CSD%CIC filter
设计了一种Σ-Δ A/D转换器中的数字抽取滤波器.该滤波器应用于音频范围,采用多级多采样率的结构,由梳状滤波器、补偿滤波器以及两个半带滤波器组成.滤波器系数用标准符号编码实现,减少了乘法单元的使用.采用Simulink模拟过采样128倍的4位调制器输出;用Verilog编写用于测试的滤波器代码.在Matlab中分析滤波器输出码流,得到的信噪比为101 dB,能够满足高端音频A/D转换器的要求.
設計瞭一種Σ-Δ A/D轉換器中的數字抽取濾波器.該濾波器應用于音頻範圍,採用多級多採樣率的結構,由梳狀濾波器、補償濾波器以及兩箇半帶濾波器組成.濾波器繫數用標準符號編碼實現,減少瞭乘法單元的使用.採用Simulink模擬過採樣128倍的4位調製器輸齣;用Verilog編寫用于測試的濾波器代碼.在Matlab中分析濾波器輸齣碼流,得到的信譟比為101 dB,能夠滿足高耑音頻A/D轉換器的要求.
설계료일충Σ-Δ A/D전환기중적수자추취려파기.해려파기응용우음빈범위,채용다급다채양솔적결구,유소상려파기、보상려파기이급량개반대려파기조성.려파기계수용표준부호편마실현,감소료승법단원적사용.채용Simulink모의과채양128배적4위조제기수출;용Verilog편사용우측시적려파기대마.재Matlab중분석려파기수출마류,득도적신조비위101 dB,능구만족고단음빈A/D전환기적요구.
A digital decimation filter in Σ-Δ A/D converter for audio applications was designed. The filter has a multistage and multi-rate structure consisting of a cascaded-integrator-comb (CIC) filter, a compensation filter and two half-band filters. To reduce the number of multiplication units, coefficients of the filter were encoded by canonical-signed-digital (CSD). Filter code for testing was written in Verilog, and output of the 128-time oversampling 4-bit modulator was simulated with Simulink. Results showed that the filter had an SNR of 101 dB, which is suitable for high-end audio applications.
