CAJ | 학술논문

提出了一种有效降低扫描测试功耗的设计方案.通过增加逻辑门结构来控制测试向量移入阶段扫描链上触发器翻转向组合逻辑电路的传播.同时,设计了时序优化算法以保持电路其他性能不发生大的改变.实验结果显示:通过采用ISCAS89基准测试程序进行分析,优化前无用动态功耗值约占总功耗的19.84%,优化后整体测试功耗降低约23%,有效地降低了无用动态功耗,并且此方案容易在已有的设计流程里实现.
제출료일충유효강저소묘측시공모적설계방안.통과증가라집문결구래공제측시향량이입계단소묘련상촉발기번전향조합라집전로적전파.동시,설계료시서우화산법이보지전로기타성능불발생대적개변.실험결과현시:통과채용ISCAS89기준측시정서진행분석,우화전무용동태공모치약점총공모적19.84%,우화후정체측시공모강저약23%,유효지강저료무용동태공모,병차차방안용역재이유적설계류정리실현.
The scan-based testing method is often used to solve the problems of testing sequential logic, and its application is limited for the high-power operation characteristics. This paper proposed an effective scheme to reduce the scan-based test power to prevent the transitions of scan chains from reflecting into the combinational logic circuit lines by adding some logic gates. Then, we introduced an optimizational arithmetic ensuring other performances of the chip. The experiment results of ISCAS89 benchmark have shown that the useless dynamic power consumption accounts for about 19.84% of the total power consumption, while the overall test power consumption has been reduced by approximately 23% after optimization. This mechanism effectively reduces the unwanted dynamics power consumption, and it is easier to implement by means of the existing methods.