CAJ | 학술논문

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.
제출료일충신적준정태단상능량회수라집,기불동우이왕적능량회수라집,진정실현료단상공솔시종,차불수요임하액외적보조공제시종,불단강저료능모,경대대간화료시종수적설계.해라집환가이체도량상능량회수라집소구유적속도.설계료일개8위대수초전진위가법기,병분별용전통적정태CMOS라집、종공CMOS절열라집(전형적단상능량회수라집)화준정태단상능량회수라집실현.채용128조수궤산생적수입측시향량적방진결과표명:수입빈솔위10MHz시,준정태능량회수라집적능모부부시전통정태CMOS라집적45%;당수입빈솔대우2MHz시,가이획득비시종공CMOS절열라집경저적능모.
This paper presents a new quasi-static single-phase energy recovery logic(QSSERL),which unlike any other existing adiabatic logic family,uses a single sinusoidal supply-clock without additional timing control voltages.This not only ensures lower energy dissipation,but also simplifies the clock design,which would be otherwise more complicated due to the signal synchronization requirement.It is demonstrated that QSSERL circuits operate as fast as conventional two-phase energy recovery logic counterparts.Simulation with an 8bit logarithmic lookahead adder(LLA)using static CMOS,clocked CMOS adiabatic logic(CAL,an existing typical single-phase energy recovery logic),and QSSERL,under 128 randomly generated input vectors,shows that the power consumption of the QSSERL adder is only 45% of that of the conventional static CMOS counterpart at 10MHz,and the QSSERL adder achieves better energy efficiency than CAL when the input frequency finput is larger than 2MHz.