CAJ | 학술논문

MAX-LOG-MAP是Turbo码译码算法的简化算法，本文提出了该算法的并行阵列集成电路实现结构，给出阵列的数据流向和译码算法在阵列中的计算过程，分析了阵列结点联接关系和数据存贮结构，以及数据运算之间的简单时序关系.通过计算机仿真，证明了这种并行实现结构的正确性.
MAX-LOG-MAP시Turbo마역마산법적간화산법，본문제출료해산법적병행진렬집성전로실현결구，급출진렬적수거류향화역마산법재진렬중적계산과정，분석료진렬결점련접관계화수거존저결구，이급수거운산지간적간단시서관계.통과계산궤방진，증명료저충병행실현결구적정학성.
The Max-Log-MAP algorithm(MLM)is a simplified version for thedecoding of Turbo codes.Architecture of parallel array is suggested based on the MLM algorithm and is easy to implement by VLSI.The data flow directions and the computation procedures of the algorithm structure are obtained,the relations among the nodes and data frames are analyzed and the simple time sequencing of data operations are given.The architecture is justified by computer simulation.