计算机工程
計算機工程
계산궤공정
COMPUTER ENGINEERING
2010年
6期
236-238
,共3页
No.7信令系统%初始定位过程%填充信号单元过滤%现场可编程门阵列
No.7信令繫統%初始定位過程%填充信號單元過濾%現場可編程門陣列
No.7신령계통%초시정위과정%전충신호단원과려%현장가편정문진렬
No.7 signaling system%process of initial aligning%Fill-in Signal Unit(FISU)filter%Field-Programmable Gate Array(FPGA)
针对CPU处理填充信号单元(FISU)存在的缺陷,分析No.7信令系统的初始定位和FISU处理过程,提出一种基于FPGA实现FISU过滤的设计方案,给出实现的原理框图、FPGA与CPU之间的通信机制和信号处理流程,使用ISE和ModelSim软件进行仿真.仿真结果表明该方案是正确、可行和有效的.
針對CPU處理填充信號單元(FISU)存在的缺陷,分析No.7信令繫統的初始定位和FISU處理過程,提齣一種基于FPGA實現FISU過濾的設計方案,給齣實現的原理框圖、FPGA與CPU之間的通信機製和信號處理流程,使用ISE和ModelSim軟件進行倣真.倣真結果錶明該方案是正確、可行和有效的.
침대CPU처리전충신호단원(FISU)존재적결함,분석No.7신령계통적초시정위화FISU처리과정,제출일충기우FPGA실현FISU과려적설계방안,급출실현적원리광도、FPGA여CPU지간적통신궤제화신호처리류정,사용ISE화ModelSim연건진행방진.방진결과표명해방안시정학、가행화유효적.
In allusion to the disadvantage of processing Fill-in Signal Unit(FISU) using CPU,on the basis of analyzing the process of initial aligning and HSU processing in No.7 signaling system,a new design scheme adopting Field-Programmable Gate Array(FPGA) to achieve FISU filter is put forward.The principle figures,communication mechanism between FPGA and CPU,and signal processing flow charts are carded out.ISE and ModelSim software are used to achieve simulation.Simulation result proves that the scheme is correct,feasible and effective.
