CAJ | 학술논문

介绍了一种适用于Viterbi解码器的异步ACS(加法器-比较器-选择器)的设计.它采用异步握手信号取代了同步电路中的整体时钟.给出了一种异步实现结构的异步加法单元、异步比较单元和异步选择单元电路.采用全定制设计方法设计了一个异步4-bit ACS,并通过0.6μm CMOS工艺进行投片验证.经过测试,芯片在工作电压5V,工作频率20MHz时的功耗为75.5mW.由于采用异步控制,芯片在"睡眠"状态待机时不消耗动态功耗.芯片的平均响应时间为19.18ns,仅为最差响应时间23.37ns的82%.通过与相同工艺下的同步4-bit ACS在功耗和性能方面仿真结果的比较,可见异步ACS较同步ACS具有优势.
개소료일충괄용우Viterbi해마기적이보ACS(가법기-비교기-선택기)적설계.타채용이보악수신호취대료동보전로중적정체시종.급출료일충이보실현결구적이보가법단원、이보비교단원화이보선택단원전로.채용전정제설계방법설계료일개이보4-bit ACS,병통과0.6μm CMOS공예진행투편험증.경과측시,심편재공작전압5V,공작빈솔20MHz시적공모위75.5mW.유우채용이보공제,심편재"수면"상태대궤시불소모동태공모.심편적평균향응시간위19.18ns,부위최차향응시간23.37ns적82%.통과여상동공예하적동보4-bit ACS재공모화성능방면방진결과적비교,가견이보ACS교동보ACS구유우세.
A novel asynchronous ACS(add-compare-select) processor for Viterbi decoder is described. It is controlled by local handshake signals instead of the globe clock. The circuits of asynchronous adder unit,asynchronous comparator unit, and asynchronous selector unit are proposed. A full-custom design of asynchronous 4-bit ACS processor is fabricated in CSMC-HJ 0.6μm CMOS 2P2M mixed-mode process. At a supply voltage of 5V, when it operates at 20 MHz, the power consumption is 75.5mW. The processor has no dynamic power consumption when it awaits an opportunity in sleep mode. The results of performance test of asynchronous 4-bit ACS processor show that the average case response time 19. 18ns is only 82% of the worst-case response time 23. 37ns. Compared with the synchronous 4bit ACS processor in power consumption and performance by simulation,it reveals that the asynchronous ACS processor has some advantages than the synchronous one.