CAJ | 학술논문

　　zw100处理器是西北工业大学和某研究所共同研制的采用 MCU-DSP 相融合架构的32位数字信号处理器。提出一种多发射多流水线结构来进行数字信号处理器的微体系结构设计，使该处理器同时具备了 RISC load /store 体系结构、DSP 的计算能力和 MCU 的实时控制能力等特点。从 zw100处理器指令集设计出发，首先介绍了该处理器架构和主要单元，然后重点讨论了基于多发射多流水线结构的指令调度策略、相邻指令耦合关系与发射机制、多发射条件下流水线相关的处理等。最后，对设计进行了仿真验证，并给出综合结果。目前，该处理器已采用 TSMC 65nm CMOS 工艺流片成功，频率达到500 MHz，达到2G MAC/s 的运算能力，性能指标满足设计要求。
　　zw100처리기시서북공업대학화모연구소공동연제적채용 MCU-DSP 상융합가구적32위수자신호처리기。제출일충다발사다류수선결구래진행수자신호처리기적미체계결구설계，사해처리기동시구비료 RISC load /store 체계결구、DSP 적계산능력화 MCU 적실시공제능력등특점。종 zw100처리기지령집설계출발，수선개소료해처리기가구화주요단원，연후중점토론료기우다발사다류수선결구적지령조도책략、상린지령우합관계여발사궤제、다발사조건하류수선상관적처리등。최후，대설계진행료방진험증，병급출종합결과。목전，해처리기이채용 TSMC 65nm CMOS 공예류편성공，빈솔체도500 MHz，체도2G MAC/s 적운산능력，성능지표만족설계요구。
A 32-bit digital signal processor(DSP),which is based on MCU-DSP architecture is presented.A smart micro-architecture is proposed with the distinguishing features of multi -issue and multi-pipeline.It helps DSP chip make a balance among low power, high performance digital signal process and real -time response.The key point of the architecture is that the dynamical instruction dispatching scans the dependence relationship between two or a -mong three adjacent instructions in the instruction queue and then decides the way of instruction issue .If the in-structions are distributed in some special way , the fetch instruction unit is allowed to dispatch three instructions into three independent pipelines in parallel at the same time , otherwise they must to dispatch in sequence .Subsection 3.1 of the full paper describes how we verify the design of our zw 100 DSP chip and subsection 3.2 describes how we analyze its logic synthesis capability .The DSP chip is fabricated with TSMC 65nm CMOS technology; the core frequency is 500 MHz and operational capability attains 2G MAC/s.