CAJ | 학술논문

迄今为止，SDRAM存储器的扩容完全依赖于半导体工艺水平的升级，而提速取决于对时钟的利用方式。DDR3 SDRAM已达8倍速率，再提速已很困难。提出一种新型串行访问的SDDR存储器结构和片内串行只写总线，将DDR存储器封装成消息连接的构件，将访问存储器的命令、地址和数据等信息打成消息报包，经片内串行只写总线与构件化的DDR存储器交换信息。 SDDR存储器减少了引脚，连接简单并且抗干扰能力强、可靠性高，易于扩容和进一步提升时钟速率，具有明显的实用前景。
흘금위지，SDRAM존저기적확용완전의뢰우반도체공예수평적승급，이제속취결우대시종적이용방식。DDR3 SDRAM이체8배속솔，재제속이흔곤난。제출일충신형천행방문적SDDR존저기결구화편내천행지사총선，장DDR존저기봉장성소식련접적구건，장방문존저기적명령、지지화수거등신식타성소식보포，경편내천행지사총선여구건화적DDR존저기교환신식。 SDDR존저기감소료인각，련접간단병차항간우능력강、가고성고，역우확용화진일보제승시종속솔，구유명현적실용전경。
So far SDRAM memory expansion is entirely dependent on the upgrade of semiconductor technology,and the speed-up is up to the clock utilization pattern .The speed of DDR3 SDRAM has been increased by a factor of 8,hence the further improvement is extremely difficult .A novel serial access SDDR memory structure and on-chip serial only write bus are presented in this paper,encapsulating the DDR memory into components connected by message,packaging such information of the accessed memory as command,address and data and so forth into message packet and exchanging information through on-chip serial only write bus and component-based DDR memory .SDDR memory reduces the number of pins,has simple connection,high anti-interference ability and reliability,and is easy for expansion and improving the clock rate further . Therefore,it has obvious practical prospects .