CAJ | 학술논문

针对分组密码算法SM4中加解密算法与密钥扩展算法的相似性，提出一种将加解密模块与密钥扩展模块复用的基本架构，通过对具体实现结构的分析与选择，使控制逻辑复杂度、复用模块复杂度以及系统吞吐量之间得到权衡。基于该架构设计SM4加解密IP核，在现场可编程门阵列上占用的资源仅为传统设计的55%，基于SMIC 0.18μm数字CMOS工艺的综合结果显示，仅用0.079 mm2即可实现100 Mb/s的数据吞吐量。实验结果表明，该结构可以有效地降低SM4算法的实现复杂度。
침대분조밀마산법SM4중가해밀산법여밀약확전산법적상사성，제출일충장가해밀모괴여밀약확전모괴복용적기본가구，통과대구체실현결구적분석여선택，사공제라집복잡도、복용모괴복잡도이급계통탄토량지간득도권형。기우해가구설계SM4가해밀IP핵，재현장가편정문진렬상점용적자원부위전통설계적55%，기우SMIC 0.18μm수자CMOS공예적종합결과현시，부용0.079 mm2즉가실현100 Mb/s적수거탄토량。실험결과표명，해결구가이유효지강저SM4산법적실현복잡도。
A basic architecture is proposed for reducing the implementation complexity of SM4 block cipher. The architecture reuses the hardware of encryption/decryption and key expansion module because the encryption/decryption algorithm is very similar with the key expansion algorithm. Optimum trade-off among control-logic complexity, reused-module complexity and throughput is realized through careful analysis and choose of specific realization. A SM4 cipher IP is designed based on this architecture. The designed IP’s cost is only 55% of the traditional design in Field Programmable Gate Array(FPGA). The IP is also synthesized under the SMIC 0.18 μm CMOS process. Its area is 0.079 mm2 with 100 Mb/s throughput. Experimental results of synthesis show that the proposed architecture can reduce the implementation complexity of SM4 block cipher efficiently.