CAJ | 학술논문

鉴于传统的多导联脑电图机双核控制采集系统中主控器ARM与SDRAM及FPGA的通讯流程繁琐重复，传输效率低，数据吞吐量小等缺陷，提出了一种基于FPGA的高速多通道实时同步采集系统方案，将缓存SDRAM交由FPGA控制并通过程序将其“内部FIFO化”，通过SDRAM前后两对FIFO的乒乓操作实现SDRAM的异步时钟同时读写，保证FPGA与ARM接口处数据的不间断，并通过简洁严谨的并行接口协议实现FPGA和ARM的高效率通信，最终将FPGA和SDRAM从物理上等效成一块“可自动采集数据的SDRAM”。测试表明，该方案避免了数据转移过程中的重复拷贝以及数据转移复杂的操作缺陷，提高数据吞吐量以及转移速率，满足了256导联脑电图的各项设计指标，采样频率可达20 kHz，甚至更高。
감우전통적다도련뇌전도궤쌍핵공제채집계통중주공기ARM여SDRAM급FPGA적통신류정번쇄중복，전수효솔저，수거탄토량소등결함，제출료일충기우FPGA적고속다통도실시동보채집계통방안，장완존SDRAM교유FPGA공제병통과정서장기“내부FIFO화”，통과SDRAM전후량대FIFO적핑퐁조작실현SDRAM적이보시종동시독사，보증FPGA여ARM접구처수거적불간단，병통과간길엄근적병행접구협의실현FPGA화ARM적고효솔통신，최종장FPGA화SDRAM종물리상등효성일괴“가자동채집수거적SDRAM”。측시표명，해방안피면료수거전이과정중적중복고패이급수거전이복잡적조작결함，제고수거탄토량이급전이속솔，만족료256도련뇌전도적각항설계지표，채양빈솔가체20 kHz，심지경고。
In view of the flaws of repeated and cumbersome communication process , inefficiency and small data throughput of the traditional dual-core control acquisition system of multi-lead EEG machine , it advances a high speed , multi-channel and real-time synchronous acquisition system , based on FPGA . The SDRAM is mainly controlled by FPGA which FIFO-internalizes the SDRAM via the program to a-chieve the asynchronous clock reading-while-writing of the SDRAM by the ping pong operation of two pairs of FIFO of SDRAM, which ensures the ongoing of interface's data transmission between FPGA and ARM and efficient communication by concise and rigorous parallel interface agreements .The FPGA and SDRAM can be equivalent to a SDRAM which can automatically collect data .Tests show that this system avoids the repeated copy of transfer process and redundant complex data transfer operation , and improves the data throughput and transfer rate , which meets the requirement for the design indexes of 256-lead EEG machine with the sample frequency up to 20 kHz or even higher .