CAJ | 학술논문

描述了在电信级以太网芯片中实现BFD快速检测与定时器协商机制的逻辑设计过程，并将硬件逻辑在FP-GA仿真芯片中进行了验证。验证了单纯硬件逻辑实现BFD定时器协商机制的可行性，该机制使用软硬件联合设计的改进方法，能够在节约硬件资源的前提下，发挥硬件的速度优势和软件的灵活优势，实现可靠的BFD时间协商过程与快速检测机制。此改进设计经过使用软件和硬件的联合验证，结果表明能够达到预期的效果，并能够实现商业应用。
묘술료재전신급이태망심편중실현BFD쾌속검측여정시기협상궤제적라집설계과정，병장경건라집재FP-GA방진심편중진행료험증。험증료단순경건라집실현BFD정시기협상궤제적가행성，해궤제사용연경건연합설계적개진방법，능구재절약경건자원적전제하，발휘경건적속도우세화연건적령활우세，실현가고적BFD시간협상과정여쾌속검측궤제。차개진설계경과사용연건화경건적연합험증，결과표명능구체도예기적효과，병능구실현상업응용。
This paper describes an improved design of BFD fast detection and timer negotiation in ASIC .We first provide the basic design of timer negotiation in hardware and prove the feasibility of ASIC logic .And the modified design uses software to realize slower timer negotiation mechanism but uses hardware to realize fast bidirectional detection .All de-signs are proved reliable by FPGA simulation .The design can take advantage of hardware to realize fast failure detection with software aids and reduce hardware cost which can be used commercially .