CAJ | 학술논문

提出了一种适用于高速小尺寸像素的列级ADC，该ADC采用单斜ADC(single-slope ADC，SS ADC)与逐次逼近ADC(successive-approximation ADC，SA ADC)相结合的方式在提高模数转换速度的同时减小了芯片面积. SS ADC实现5位粗量化，SA ADC实现5位细量化，SA ADC中5位分段电容DAC的桥接电容采用单位电容并利用区间交叠方式实现了误差校正．采用GSMC 0.18,μm 1P4M标准CMOS工艺对电路进行设计，仿真结果表明：所提出的列级ADC在167,kHz/s采样率和3.3,V电源电压下，有效位数9.81，每列功耗0.132,mW，速度比传统SS ADC提高了22倍．
제출료일충괄용우고속소척촌상소적렬급ADC，해ADC채용단사ADC(single-slope ADC，SS ADC)여축차핍근ADC(successive-approximation ADC，SA ADC)상결합적방식재제고모수전환속도적동시감소료심편면적. SS ADC실현5위조양화，SA ADC실현5위세양화，SA ADC중5위분단전용DAC적교접전용채용단위전용병이용구간교첩방식실현료오차교정．채용GSMC 0.18,μm 1P4M표준CMOS공예대전로진행설계，방진결과표명：소제출적렬급ADC재167,kHz/s채양솔화3.3,V전원전압하，유효위수9.81，매렬공모0.132,mW，속도비전통SS ADC제고료22배．
A column-parallel ADC for high speed and small pixel size CMOS image sensor is proposed. The proposed ADC not only improves speed but also decreases chip area by combining single-slope ADC(SS ADC)with successive-approximation ADC(SA ADC). SS ADC converts the upper five bits,and SA ADC converts the lower five bits. The coupling capacitor of 5-bit segmented capacitive DAC in SA ADC is a unit capacitor. In addition,error correction is realized by interval overlap. The proposed ADC,which is designed in 0.18,μm 1P4M standard CMOS process, shows an effective bit number of 9.81 at 167,kHz/s. It dissipates 0.132,mW with a 3.3,V power supply. The speed is 22,times faster than that of the conventional SS ADC.