CAJ | 학술논문

针对具有多种逻辑块和互连线结构的现代主流现场可编程门阵列(FPGA)，给出一种通用的 FPGA 结构描述方法。根据FPGA 硬件版图由几类重复单元在水平和垂直方向复制拼接而成的特点，提出基于层次化重复单元的 FPGA 结构模型，在该模型的基础上，通过定义一套完整的语法来描述FPGA。实验结果表明，该方法能正确描述FPGA硬件信息，并配合FPGA软件系统正常工作，具有结构通用和描述文件小的优点。
침대구유다충라집괴화호련선결구적현대주류현장가편정문진렬(FPGA)，급출일충통용적 FPGA 결구묘술방법。근거FPGA 경건판도유궤류중복단원재수평화수직방향복제병접이성적특점，제출기우층차화중복단원적 FPGA 결구모형，재해모형적기출상，통과정의일투완정적어법래묘술FPGA。실험결과표명，해방법능정학묘술FPGA경건신식，병배합FPGA연건계통정상공작，구유결구통용화묘술문건소적우점。
Aiming at modern mainstream Field Programmable Gate Array(FPGA) with diverse logic blocks and interconnect lines, this paper proposes a universe FPGA architecture description method. Considering the fact that tiles are actually copied and pieced together to form the overall FPGA hardware layout, this paper proposes an FPGA architecture model based on hierarchical tile. According to the model, this paper also defines a set of complete and detailed syntactic rules to describe the FPGA architecture. Experimental results show that the description method can delineate FPGA hardware information, and work correctly with FPGA software system. It has common architecture and is small in size.