CAJ | 학술논문

埋入堆叠芯片技术在实现封装小型化的同时，增加了封装电学设计的复杂性。以一个数字系统为例，详细阐述了埋入堆叠芯片封装结构的电学设计过程。利用电磁仿真软件提取了该封装结构的寄生参数，并通过S参数、延时、反射分析，确定长绑定线为影响链路信号质量的关键因素，其影响直接限制了埋入堆叠芯片技术的应用范围。运用RLC传输线模型分析了长绑定线造成大的信号质量衰减的原因。最后，提出了一种大幅减短绑定线长度并提升链路电学性能的优化结构，拓展了此技术在高速领域的应用。眼图的对比结构表明，新结构能降低链路的阻抗失配，减小信号延时，并大大改善高速信号的质量。
매입퇴첩심편기술재실현봉장소형화적동시，증가료봉장전학설계적복잡성。이일개수자계통위례，상세천술료매입퇴첩심편봉장결구적전학설계과정。이용전자방진연건제취료해봉장결구적기생삼수，병통과S삼수、연시、반사분석，학정장방정선위영향련로신호질량적관건인소，기영향직접한제료매입퇴첩심편기술적응용범위。운용RLC전수선모형분석료장방정선조성대적신호질량쇠감적원인。최후，제출료일충대폭감단방정선장도병제승련로전학성능적우화결구，탁전료차기술재고속영역적응용。안도적대비결구표명，신결구능강저련로적조항실배，감소신호연시，병대대개선고속신호적질량。
The embedded stacked-die technique miniaturizes the package outline of a multi-chip system,but increases the electrical design complexity of the package structure. The electrical simulation and optimization process of the package design of a digital system which utilized this technique is elaborated in this paper. The parasitic parameters of the package structure were extracted by electromagnetic simulation software. By S-parameter,time delay and reflection analysis,the bonding wires were de-termined to be the critical factors that affect the signal quality and significantly limit the application of embedded stacked-chip technique. The phenomena were then explained by RLC model. In the last,an optimized structure was proposed to reduce the length of bonding wires and enhance the electrical performance of the whole channel. The contrast result according to the eye dia-gram indicates that the new structure has reduced the link impedance mismatching and time delay,and improved the quality of high-speed signals.