东南大学学报(英文版)
東南大學學報(英文版)
동남대학학보(영문판)
JOURNAL OF SOUTHEAST UNIVERSITY
2013年
3期
242-246
,共5页
雷雪梅%王志功%王科平%沈连丰
雷雪梅%王誌功%王科平%瀋連豐
뢰설매%왕지공%왕과평%침련봉
频率综合器%宽带压控振荡器%吞吐脉冲分频器%低相位噪声
頻率綜閤器%寬帶壓控振盪器%吞吐脈遲分頻器%低相位譟聲
빈솔종합기%관대압공진탕기%탄토맥충분빈기%저상위조성
frequency synthesizer%wideband voltage-control oscillator%pulse swallow frequency divider%low phase noise
介绍了一种应用于宽带低相位噪声的频率综合器.此频率综合器为兼容DRM,DAB,AM和FM的射频前端提供本振信号.为了覆盖所有频段的信号,提出了一种新的频率规划和系统结构.此频率综合器包含宽带低功耗低相位噪声的VCO和高速宽带低功耗的大分频比吞吐脉冲分频器等模块.所设计的频率综合器应用中芯国际的0.18μm RF CMOS工艺进行了流片实现.整个芯片面积为1425μm ×795μm,包括测试驱动电路和焊盘.测试结果表明,压控振荡器振荡频率范围为2.27~3.57 GHz.在频偏为1 MHz时,其相位噪声为120.22 dBc/Hz;吐脉冲分频器的工作频率范围为0.9~3.4 GHz;在频偏为10 kHz时,锁相环内的相位噪声为-59.52 dBc/Hz,完全满足DRM/DAB/AM/FM射频前端的要求.此频率综合器在1.8 V的电源电压下,其功耗为47 mW(包括测试驱动的功耗).
介紹瞭一種應用于寬帶低相位譟聲的頻率綜閤器.此頻率綜閤器為兼容DRM,DAB,AM和FM的射頻前耑提供本振信號.為瞭覆蓋所有頻段的信號,提齣瞭一種新的頻率規劃和繫統結構.此頻率綜閤器包含寬帶低功耗低相位譟聲的VCO和高速寬帶低功耗的大分頻比吞吐脈遲分頻器等模塊.所設計的頻率綜閤器應用中芯國際的0.18μm RF CMOS工藝進行瞭流片實現.整箇芯片麵積為1425μm ×795μm,包括測試驅動電路和銲盤.測試結果錶明,壓控振盪器振盪頻率範圍為2.27~3.57 GHz.在頻偏為1 MHz時,其相位譟聲為120.22 dBc/Hz;吐脈遲分頻器的工作頻率範圍為0.9~3.4 GHz;在頻偏為10 kHz時,鎖相環內的相位譟聲為-59.52 dBc/Hz,完全滿足DRM/DAB/AM/FM射頻前耑的要求.此頻率綜閤器在1.8 V的電源電壓下,其功耗為47 mW(包括測試驅動的功耗).
개소료일충응용우관대저상위조성적빈솔종합기.차빈솔종합기위겸용DRM,DAB,AM화FM적사빈전단제공본진신호.위료복개소유빈단적신호,제출료일충신적빈솔규화화계통결구.차빈솔종합기포함관대저공모저상위조성적VCO화고속관대저공모적대분빈비탄토맥충분빈기등모괴.소설계적빈솔종합기응용중심국제적0.18μm RF CMOS공예진행료류편실현.정개심편면적위1425μm ×795μm,포괄측시구동전로화한반.측시결과표명,압공진탕기진탕빈솔범위위2.27~3.57 GHz.재빈편위1 MHz시,기상위조성위120.22 dBc/Hz;토맥충분빈기적공작빈솔범위위0.9~3.4 GHz;재빈편위10 kHz시,쇄상배내적상위조성위-59.52 dBc/Hz,완전만족DRM/DAB/AM/FM사빈전단적요구.차빈솔종합기재1.8 V적전원전압하,기공모위47 mW(포괄측시구동적공모).
This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC's 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.