CAJ | 학술논문

介绍了一种简洁可靠的数字锁相频综快速跳频的原理、组成及实现，采用电阻开关网络对锁相环(PLL)进行预置，在保证相位噪声、杂散等指标不变的前提下提高了跳频速度，并通过了实际的测试。该方法实现了锁相电路跳频过程中的快速预置，加速了频综的跳频速度。
개소료일충간길가고적수자쇄상빈종쾌속도빈적원리、조성급실현，채용전조개관망락대쇄상배(PLL)진행예치，재보증상위조성、잡산등지표불변적전제하제고료도빈속도，병통과료실제적측시。해방법실현료쇄상전로도빈과정중적쾌속예치，가속료빈종적도빈속도。
The fast frequency hopping principle, composition and implementation of a simple and reliable digital phase-locked frequency synthesizer is introduced. A resistance switching network is adopted for Phase-Locked Loop(PLL) presets. The hopping speed is improved under the premise of keeping the phase noise, spurs and other indicators unchanged. The actual tests indicate that the proposed method can realize the fast frequency hopping process preset of phase-locked circuit, and accelerate the frequency hopping speed.