CAJ | 학술논문

针对序列密码算法中延迟较大的插入与抽取操作，提出基于butterfly和inverse butterfly网络的可重构硬件实现方案，使其支持位宽为2n 比特的任意插入与抽取操作。并对控制信息生成算法进行深入的研究，在简化电路硬件实现的同时，大幅度提升了插入与抽取操作的处理性能。该设计已在FPGA上完成功能验证，并在CMOS 0．13μm工艺下完成综合与优化，结果表明，可重构插入与抽取单元延时小于2．7 ns，系统时钟频率达到了450 MHz。
침대서렬밀마산법중연지교대적삽입여추취조작，제출기우butterfly화inverse butterfly망락적가중구경건실현방안，사기지지위관위2n 비특적임의삽입여추취조작。병대공제신식생성산법진행심입적연구，재간화전로경건실현적동시，대폭도제승료삽입여추취조작적처이성능。해설계이재FPGA상완성공능험증，병재CMOS 0．13μm공예하완성종합여우화，결과표명，가중구삽입여추취단원연시소우2．7 ns，계통시종빈솔체도료450 MHz。
Aiming at the insert and extract operation with bigger delay in stream cipher algorithm,we present the implementation scheme for reconfigurable hardware which is based on butterfly and inverse butterfly network,and allow it to support arbitrary insert and extract opera-tions in widths of 2n bits.We also make thorough study on control bits generation algorithm,while simplify the circuit hardware,the process-ing performance of insert and extract operation is greatly improved as well.The design has been completed its function verification on FPGA and its synthesis and optimisation with CMOS 0.13 μm technology.Result shows that the reconfigurable insert and extract unit has the delay less than 2.7 ns,its system time frequency achieves 450 MHz.