CAJ | 학술논문

三维众核片上处理器的研究近年来逐渐引起了学术界的广泛关注.三维集成电路技术可以支持将不同工艺的存储器层集成到一颗芯片上,三维众核片上处理器可以集成更大的片上缓存以及主存储器.研究三维众核片上处理器存储架构,探索了集成 SRAM L2 cache层,DRAM主存储器层等,对三维众核片上处理器性能的影响.从仿真结果可知,相比集成1层L2 cache,集成2层L2 cache的三维众核片上处理器性能最大提高了55%,平均提高34%.将DRAM主存储器集成到片上最大可以提高三维众核片上处理器80%的系统性能,平均改善34.2%.
삼유음핵편상처리기적연구근년래축점인기료학술계적엄범관주.삼유집성전로기술가이지지장불동공예적존저기층집성도일과심편상,삼유음핵편상처리기가이집성경대적편상완존이급주존저기.연구삼유음핵편상처리기존저가구,탐색료집성 SRAM L2 cache층,DRAM주존저기층등,대삼유음핵편상처리기성능적영향.종방진결과가지,상비집성1층L2 cache,집성2층L2 cache적삼유음핵편상처리기성능최대제고료55%,평균제고34%.장DRAM주존저기집성도편상최대가이제고삼유음핵편상처리기80%적계통성능,평균개선34.2%.
The purpose of this paper is to study the performance improvement of memory architectures for three-di-mensional chip multi-processors(3D CMPs).As CMPs integrate more and more cores,a great deal of data access pressure is placed on the memory subsystem.Designers face the challenges of feeding enough data to a massive number of on-die cores for CMPs.Three-dimensional integrated circuits(3D ICs)can stack memories of different process technologies into the same chip.The stacking memory bandwidth can be enlarged by using fine-pitch through-silicon vias(TSVs),which can mitigate the pressure on the I/O infrastructure for CMPs.In this paper,we start with studying the potential benefit of 3D integration and the recent advantages on the research of memory ar-chitectures for 3D CMPs.Bothe large caches and main memories can be stacked in 3D CMPs.Hence,we focus on the memory architectures for 3D CMPs in two aspects,stacking cache architecture and stacking main memory architecture.3D CMPs can integrate much larger L2 caches compared to their 2D counterparts in the same area footprint.Meanwhile,the L2 caches can be several layers.We firstly explore the performance improvements of stacking SRAM L2 cache layers atop processor layers for 3D CMPs.The experimental results show that the 3D CMPs with 2 L2 cache layers can improve the performance up to 55% and 34% on average compared to that of 3D CMPs with 1 L2 cache layer.3D CMPs provide opportunities for composing future systems by integrating disparate technologies memories.The off-chip DRAM main memories can be stacked on the processor layers.We secondly study the performance benefit of integrating DRAM main memories into 3D CMPs.The experiment results show that stacking DRAM main memories can provide up to 80% and on average 34.2% performance improvement for 3D CMPs compared to the 2D CMPs with off-chip DRAM main memory.Our analysis and experimental results give a guideline to design efficient 3D CMPs with stacking SRAM L2 caches and DRAM main memories.