CAJ | 학술논문

分析了倍频器对芯片原子钟稳定度指标的影响,并以此提出了对倍频器的设计要求。介绍了国内外几种典型的原子钟倍频器,提出了一种基于撞-D调制的芯片原子钟专用锁相倍频器方案,并采用分离器件对该方案进行了验证,实现了与传统铷钟物理系统的闭环锁定,铷原子频标稳定度指标达4.7E-12/s,能满足原子钟的研制需求。基于该方案开展了倍频器芯片的设计和流片,实现了3.4GHz的芯片原子钟专用芯片,与物理系统进行联调锁定后稳定度指标达5.5E-11/s,表明该芯片可满足芯片原子钟的设计要求。
분석료배빈기대심편원자종은정도지표적영향,병이차제출료대배빈기적설계요구。개소료국내외궤충전형적원자종배빈기,제출료일충기우당-D조제적심편원자종전용쇄상배빈기방안,병채용분리기건대해방안진행료험증,실현료여전통여종물리계통적폐배쇄정,여원자빈표은정도지표체4.7E-12/s,능만족원자종적연제수구。기우해방안개전료배빈기심편적설계화류편,실현료3.4GHz적심편원자종전용심편,여물리계통진행련조쇄정후은정도지표체5.5E-11/s,표명해심편가만족심편원자종적설계요구。
By analyzing the affection on atomic clock stability, the demanding for the frequency multiplier has been offered. In comparison with several typical configurations, a novel frequency multipli-er scheme consisting of synthesizer, orthogonal mixer and DDS has been designed. Guided by the design, the first prototype fabricated with individual components has been completed; the frequency stability is 4. 7E-12/s after locking, and this design can be qualified for atomic clock. Basing on the design scheme, the special 3. 4 GHz ASIC has been fabricated, and the chip-scale atomic clock incorporated the ASIC arrived to 5. 5E-11/s, which proves that the ASIC can satisfy the design requirements of chip-scale atomic clock.