CAJ | 학술논문

高速采样技术在雷达信号处理系统中至关重要。在使用多通道串行输出AD芯片进行采样时， AD芯片输出的时钟信号与串行数据信号在传输的过程中获得了不同程度的延时，导致关键路径的时序要求不能够得到满足。为了解决上述问题，提出了一种自适应动态相位调整算法，动态调整时钟和数据的相位关系使其能够在高速条件下正确匹配；设计了基于ADS6445模数转换芯片和Virtex-5 FPGA芯片的采样系统对算法进行验证，经系统测试该算法成功将时钟变化沿对准了数据窗中心位置，大幅度提高了系统采样的准确性和稳定性。经计算，系统的采样数据有效位达到11位以上，满足雷达信号处理对数据精度的高要求。
고속채양기술재뢰체신호처리계통중지관중요。재사용다통도천행수출AD심편진행채양시， AD심편수출적시종신호여천행수거신호재전수적과정중획득료불동정도적연시，도치관건로경적시서요구불능구득도만족。위료해결상술문제，제출료일충자괄응동태상위조정산법，동태조정시종화수거적상위관계사기능구재고속조건하정학필배；설계료기우ADS6445모수전환심편화Virtex-5 FPGA심편적채양계통대산법진행험증，경계통측시해산법성공장시종변화연대준료수거창중심위치，대폭도제고료계통채양적준학성화은정성。경계산，계통적채양수거유효위체도11위이상，만족뢰체신호처리대수거정도적고요구。
High speed sampling technology is extremely important in radar signal processing systems, some systems employ multi-channel serial-output AD ( Analog to Digital) chips to sample data, because the de-lays of clock signal and serial data signal are not equal during the transmission, the timing constraints of crucial paths couldn’t be matched. To solve above-mentioned problem,this paper presents a self-adjust dynamic phase modulation algorithm which modulates the phase relationship between clock and data to make sure they match correctly in high speed conditions. A sampling system based on ADS6445 analog to digital chip and Virtex-5 FPGA ( Field Programmable Gate Array ) chip is designed to validate the algo-rithm. Test shows the algorithm successfully matches the clock edge to the middle of data window and large-ly improves the stability and veracity of the system. The ENOB(Effect Number of Bits) of the system is higher than 11,so the system completely meets the high data precision demand of radar signal processing.