电子设计工程
電子設計工程
전자설계공정
ELECTRONIC DESIGN ENGINEERING
2014年
18期
65-68,73
,共5页
SOPC%FPGA%Nios II%数字示波器
SOPC%FPGA%Nios II%數字示波器
SOPC%FPGA%Nios II%수자시파기
system on a programmable chip%field programmable gate Array%Nios II%digital storage oscilloscope
为了方便外场测量及维护工作,提出了一种基于片上可编程系统(System On Programmable Chip)技术的便携式数字示波器实现方案。与传统FPGA作为数据存取处理MCU作为显示控制的设计方案不同,基于SOPC的便携式数字示波器设计方案通过在FPGA中嵌入Nios II系统,作为CPU实现对LCD波形及参数显示控制;利用FPGA的逻辑资源,设计采样数据的存取控制模块,实现采样信号的触发存取功能。实际测试结果表明,该便携式数字示波器信号幅度测量范围为50 mV~20 V,测量误差小于4%,频率测量范围为1 Hz~50 MHz,测量误差小于2.5%。
為瞭方便外場測量及維護工作,提齣瞭一種基于片上可編程繫統(System On Programmable Chip)技術的便攜式數字示波器實現方案。與傳統FPGA作為數據存取處理MCU作為顯示控製的設計方案不同,基于SOPC的便攜式數字示波器設計方案通過在FPGA中嵌入Nios II繫統,作為CPU實現對LCD波形及參數顯示控製;利用FPGA的邏輯資源,設計採樣數據的存取控製模塊,實現採樣信號的觸髮存取功能。實際測試結果錶明,該便攜式數字示波器信號幅度測量範圍為50 mV~20 V,測量誤差小于4%,頻率測量範圍為1 Hz~50 MHz,測量誤差小于2.5%。
위료방편외장측량급유호공작,제출료일충기우편상가편정계통(System On Programmable Chip)기술적편휴식수자시파기실현방안。여전통FPGA작위수거존취처리MCU작위현시공제적설계방안불동,기우SOPC적편휴식수자시파기설계방안통과재FPGA중감입Nios II계통,작위CPU실현대LCD파형급삼수현시공제;이용FPGA적라집자원,설계채양수거적존취공제모괴,실현채양신호적촉발존취공능。실제측시결과표명,해편휴식수자시파기신호폭도측량범위위50 mV~20 V,측량오차소우4%,빈솔측량범위위1 Hz~50 MHz,측량오차소우2.5%。
To facilitate the external measurements and maintenance tasks, we proposed an implementation of portable digital storage oscilloscope system, based on programmable chip (System on Programmable Chip) technology. Unlike the traditional design of FPGA for date access process and MCU for display control, the design of portable digital oscilloscope based on SOPC embeds Nios II into FPGA. The embedded system acts as a CPU which controls display of LCD waveform and parameters. In addition, FPGA logical resources are used to design access control module of sampling data and realize trigger access function of that. The practical test results indicate that for the portable digital oscilloscope, the measurement range of signal amplitude is 50 mV~20 V with measuring error less than 4%and the measurement range of frequency is 1 Hz~50 MHz with measuring error less than 2.5%.