CAJ | 학술논문

针对八通道采样器AD9252的高速串行数据接口的特点,提出了一种基于FPGA时序约束的高速解串方法。使用Xilinx公司的FPGA接收高速串行数据,利用FPGA内部的时钟管理模块DCM、位置约束和底层工具Planahead实现高速串并转换中数据建立时间和保持时间的要求,实现并行数据的正确输出。最后通过功能测试和时序测试,验证了设计的正确性。此方法可适用于高端和低端FPGA,提高了系统设计的灵活性,降低了系统的成本。
침대팔통도채양기AD9252적고속천행수거접구적특점,제출료일충기우FPGA시서약속적고속해천방법。사용Xilinx공사적FPGA접수고속천행수거,이용FPGA내부적시종관리모괴DCM、위치약속화저층공구Planahead실현고속천병전환중수거건립시간화보지시간적요구,실현병행수거적정학수출。최후통과공능측시화시서측시,험증료설계적정학성。차방법가괄용우고단화저단FPGA,제고료계통설계적령활성,강저료계통적성본。
According to the characteristics of high-speed serial data in eight-channel sampler AD9252,a method which is based on time constraint of FPGA is presented. In this method,the Xilinx FPGA is used to receive the sampling serial data. In order to achieve the setup time and hold time of serial-parallel conver-sion,the digital clock management( DCM) module,location constraints and Planahead are used. The de-sign is verified by functional and timing test. Because the method is suitable for high-end and low-end FP-GA,the flexibility of system is improved.