计算机工程与应用
計算機工程與應用
계산궤공정여응용
COMPUTER ENGINEERING AND APPLICATIONS
2014年
3期
181-184
,共4页
马胜前%杨阳%刘娟芳
馬勝前%楊暘%劉娟芳
마성전%양양%류연방
现场可编程门阵列(FPGA)%全数字锁相环%自适应%开关电容滤波%低通滤波器
現場可編程門陣列(FPGA)%全數字鎖相環%自適應%開關電容濾波%低通濾波器
현장가편정문진렬(FPGA)%전수자쇄상배%자괄응%개관전용려파%저통려파기
Field-Programmable Gate Array(FPGA)%All Digital Phase Locked Loop(ADPLL)%adaptive%switched-capacitor filter%low pass filter
提出了一种新的基于全数字锁相环的自适应低通滤波系统的结构和实现方法。输入信号经整形后产生方波信号，方波信号经FPGA实现的全数字锁相环锁相同步倍频后，再将同步倍频信号输入到开关电容滤波器MAX295的时钟输入端，通过该时钟信号来控制滤波器的截止频率，从而实现滤波器频率的自动跟踪。介绍了系统设计原理，详细分析了FPGA实现全数字锁相环和锁相倍频的设计方法。通过实验验证了该系统的可行性和有效性，能够实现1 kHz至50 kHz的频率自跟踪倍频和滤波。
提齣瞭一種新的基于全數字鎖相環的自適應低通濾波繫統的結構和實現方法。輸入信號經整形後產生方波信號，方波信號經FPGA實現的全數字鎖相環鎖相同步倍頻後，再將同步倍頻信號輸入到開關電容濾波器MAX295的時鐘輸入耑，通過該時鐘信號來控製濾波器的截止頻率，從而實現濾波器頻率的自動跟蹤。介紹瞭繫統設計原理，詳細分析瞭FPGA實現全數字鎖相環和鎖相倍頻的設計方法。通過實驗驗證瞭該繫統的可行性和有效性，能夠實現1 kHz至50 kHz的頻率自跟蹤倍頻和濾波。
제출료일충신적기우전수자쇄상배적자괄응저통려파계통적결구화실현방법。수입신호경정형후산생방파신호，방파신호경FPGA실현적전수자쇄상배쇄상동보배빈후，재장동보배빈신호수입도개관전용려파기MAX295적시종수입단，통과해시종신호래공제려파기적절지빈솔，종이실현려파기빈솔적자동근종。개소료계통설계원리，상세분석료FPGA실현전수자쇄상배화쇄상배빈적설계방법。통과실험험증료해계통적가행성화유효성，능구실현1 kHz지50 kHz적빈솔자근종배빈화려파。
This paper presents the structure and implementation of an adaptive low-pass filter system based on ADPLL (All Digital Phase Locked Loop). The input signal is converted into square signal after shaping. The square signal is phase-locked and transformed into synchronous frequency multiplication signal after passing through the ADPLL based on FPGA. The frequency multiplication signal is input into switched-capacitor filter MAX295 as clk which can control corner frequency. The cutoff frequency of the low-pass filter is tracked automatically with the change of signal frequency. The design principle is introduced. The design method of ADPLL and phase-locked frequency multiplier based on FPGA is analyzed in detail. The experiment results illustrate that the system is feasible and effective. The system is able to realize the self-tracking of double-frequency and filtering when the frequency varies from 1 kHz to 50 kHz.
