CAJ | 학술논문

提出了一种并行的可配置HEVC熵编码的VLSI结构。通过对HEVC参考软件算法分析，针对HEVC中CABAC编码采用高度并行的语法元素处理方式，设计了针对CABAC中语法元素并行处理的硬件结构。同时采用可配置的PE-Array结构，在提高了吞吐率和计算效率的同时，平衡了VLSI设计中面积过大的问题。在SMIC 0.13μm工艺库下，进行了逻辑综合，系统总门数为16.2 K，片上存储为20.8 KB。在时钟频率300 MHz下，可处理3840×2160@30 frame/s的视频序列。
제출료일충병행적가배치HEVC적편마적VLSI결구。통과대HEVC삼고연건산법분석，침대HEVC중CABAC편마채용고도병행적어법원소처리방식，설계료침대CABAC중어법원소병행처리적경건결구。동시채용가배치적PE-Array결구，재제고료탄토솔화계산효솔적동시，평형료VLSI설계중면적과대적문제。재SMIC 0.13μm공예고하，진행료라집종합，계통총문수위16.2 K，편상존저위20.8 KB。재시종빈솔300 MHz하，가처리3840×2160@30 frame/s적시빈서렬。
VLSI architecture for parallel and configurable entropy coding of HEVC is proposed. By reference software algorithm of HEVC analysis, the CABAC encoding for HEVC syntax elements using highly parallel processing, it designs parallel processing hardware architecture for CABAC syntax elements. At the same time, the configurable PE-Array struc-ture can be used. While improving throughput and computational efficiency the problem of excessive area in VLSI design is solved. After logic synthesis using SMIC 0.13μm standard cell library, the number of gates is 16.2 K, and chip cache is 20.8 KB. This design can handle 3 840×2 160@30 frame/s under the working frequency of 300 MHz.