太赫兹科学与电子信息学报
太赫玆科學與電子信息學報
태혁자과학여전자신식학보
Information and Electronic Engineering
2013年
6期
897-901
,共5页
数据缓存%先进先出%存储单元%性能分析%现场可编程门阵列
數據緩存%先進先齣%存儲單元%性能分析%現場可編程門陣列
수거완존%선진선출%존저단원%성능분석%현장가편정문진렬
data caching%First Input First Output%Cell%performance analysis%Field Programmable Gate Array
为了在多通道数据传输中实现各通道数据的均衡与高效传输,提出一种基于现场可编程门阵列(FPGA)的多通道动态先进先出缓存设计方法。该方法通过建立小型存储单元,动态维护各通道的数据传输状态,并采用数据库索引技术,为各通道数据高速、动态地分配缓存空间。本文以 FPGA为平台,实现了该方法。仿真实验结果表明,该方法能通过较少的缓存设置,实现各个通道的均衡传输,节约存储资源,并提高各通道的数据传输效率。
為瞭在多通道數據傳輸中實現各通道數據的均衡與高效傳輸,提齣一種基于現場可編程門陣列(FPGA)的多通道動態先進先齣緩存設計方法。該方法通過建立小型存儲單元,動態維護各通道的數據傳輸狀態,併採用數據庫索引技術,為各通道數據高速、動態地分配緩存空間。本文以 FPGA為平檯,實現瞭該方法。倣真實驗結果錶明,該方法能通過較少的緩存設置,實現各箇通道的均衡傳輸,節約存儲資源,併提高各通道的數據傳輸效率。
위료재다통도수거전수중실현각통도수거적균형여고효전수,제출일충기우현장가편정문진렬(FPGA)적다통도동태선진선출완존설계방법。해방법통과건립소형존저단원,동태유호각통도적수거전수상태,병채용수거고색인기술,위각통도수거고속、동태지분배완존공간。본문이 FPGA위평태,실현료해방법。방진실험결과표명,해방법능통과교소적완존설치,실현각개통도적균형전수,절약존저자원,병제고각통도적수거전수효솔。
A multi-channel dynamic First Input First Output(FIFO) caching design method based on Field Programmable Gate Array(FPGA) is proposed in order to achieve a balanced and efficient transmission of the channel data in the process of multi-channel data transmission. The method, which is realized on FPGA platform, manages to dynamically maintain the data transmission status of each channel by establishing a small storage unit, and dynamically allocate the cache space for each channel data quickly by using the database indexing technology. Experimental results show that the method can achieve balanced transmission of each channel, save the storage resources and improve the efficiency of data transmission for each channel with fewer caching settings.