电子与封装
電子與封裝
전자여봉장
EIECTRONICS AND PACKAGING
2014年
1期
6-10
,共5页
超大面积芯片烧结%金锡共晶%去应力%可靠性试验
超大麵積芯片燒結%金錫共晶%去應力%可靠性試驗
초대면적심편소결%금석공정%거응력%가고성시험
large chip sintering%Au-Sn eutectic%stress removal%reliability test
随着半导体大功率器件的发展，芯片的散热一直是制约功率器件发展的因素之一。而器件内部散热主要是通过芯片背面向外传导，芯片焊接工艺是直接影响器件散热好坏的关键因素之一，合金焊料的一个显著优点就是其导热性能好，因此在散热要求高的大功率器件中使用较为广泛（如Au80Sn20、Au99.4Sb0.6等），但由于合金焊料烧结后会产生较大的残余应力，在尺寸大于8 mm×8 mm的芯片上，烧结工艺应用较少。文章针对11.5 mm×11.5 mm超大面积芯片进行金锡合金烧结试验，经过对应力产生的原因进行分析，从材料、封装工艺等方面采取措施来降低缓释应力，并对封装产品进行可靠性考核验证。试验结果表明，没有芯片存在裂纹、碎裂现象，产品通过了可靠性验证。
隨著半導體大功率器件的髮展，芯片的散熱一直是製約功率器件髮展的因素之一。而器件內部散熱主要是通過芯片揹麵嚮外傳導，芯片銲接工藝是直接影響器件散熱好壞的關鍵因素之一，閤金銲料的一箇顯著優點就是其導熱性能好，因此在散熱要求高的大功率器件中使用較為廣汎（如Au80Sn20、Au99.4Sb0.6等），但由于閤金銲料燒結後會產生較大的殘餘應力，在呎吋大于8 mm×8 mm的芯片上，燒結工藝應用較少。文章針對11.5 mm×11.5 mm超大麵積芯片進行金錫閤金燒結試驗，經過對應力產生的原因進行分析，從材料、封裝工藝等方麵採取措施來降低緩釋應力，併對封裝產品進行可靠性攷覈驗證。試驗結果錶明，沒有芯片存在裂紋、碎裂現象，產品通過瞭可靠性驗證。
수착반도체대공솔기건적발전，심편적산열일직시제약공솔기건발전적인소지일。이기건내부산열주요시통과심편배면향외전도，심편한접공예시직접영향기건산열호배적관건인소지일，합금한료적일개현저우점취시기도열성능호，인차재산열요구고적대공솔기건중사용교위엄범（여Au80Sn20、Au99.4Sb0.6등），단유우합금한료소결후회산생교대적잔여응력，재척촌대우8 mm×8 mm적심편상，소결공예응용교소。문장침대11.5 mm×11.5 mm초대면적심편진행금석합금소결시험，경과대응력산생적원인진행분석，종재료、봉장공예등방면채취조시래강저완석응력，병대봉장산품진행가고성고핵험증。시험결과표명，몰유심편존재렬문、쇄렬현상，산품통과료가고성험증。
With the development of semiconductor power devices, chip’s cooling of the device was one of the factors which has been restricting the power devices’ development. The device’s cooling was mainly through the internal heat conduction out of the back of the chip. The chip welding heat from the device directly affect one of the key factors is good or bad, the obvious advantages of alloy solder’s thermal conductivity is good, therefore widely used in high power devices(such as Au80Sn20, Au99.4Sb0.6, etc), but as a result of alloy solder caused large residual stress after sintering, sintering process is less application on the chip size greater than 8 mm×8 mm. In the paper, 11.5 mm×11.5 mm large chip sintering experiment was carried out uses Au-Sn alloy, through the analysis of the causes of stress, from material, packaging process, etc, to take steps to reduce stress, and veriifed the reliability assessment of packaging products. The experimental results show that there is no chip failure.
