CAJ | 학술논문

针对甚长波红外(VLWIR)探测器动态结阻抗过低、暗电流较大，且工作在高背景环境下等特点，设计了一种具有记忆功能背景抑制的32×32甚长波红外焦平面(IRFPA)读出电路。该电路采用基于高增益负反馈运放的缓冲直接注入级(BDI)结构作为输入级，大幅降低了输入阻抗，提高了注入效率，并使探测器处于稳定偏压状态。同时，该电路采用具有记忆功能的背景抑制电路，有效提高了积分时间和红外焦平面的信噪比(SNR)，改善了动态范围和对比度。基于HHNEC CZ6H 0.35μm 1P4M标准CMOS工艺，完成了电路的流片制造。实测结果表明：50 K低温下电路功能正常，输出范围大于2 V，读出速率达到2.5 MHz，RMS噪声小于0.3 mV，线性度优于99%，功耗小于100 mW。
침대심장파홍외(VLWIR)탐측기동태결조항과저、암전류교대，차공작재고배경배경하등특점，설계료일충구유기억공능배경억제적32×32심장파홍외초평면(IRFPA)독출전로。해전로채용기우고증익부반궤운방적완충직접주입급(BDI)결구작위수입급，대폭강저료수입조항，제고료주입효솔，병사탐측기처우은정편압상태。동시，해전로채용구유기억공능적배경억제전로，유효제고료적분시간화홍외초평면적신조비(SNR)，개선료동태범위화대비도。기우HHNEC CZ6H 0.35μm 1P4M표준CMOS공예，완성료전로적류편제조。실측결과표명：50 K저온하전로공능정상，수출범위대우2 V，독출속솔체도2.5 MHz，RMS조성소우0.3 mV，선성도우우99%，공모소우100 mW。
A 32í32 readout integrated circuit (ROIC) for very long wavelength (VLWIR) detector was designed, which uses buffered direct injection (BDI) unit cell as input circuit to reduce the input resistance, increase the injection efficiency of signal current, and provide precise biasing voltage to the detector. Due to very low output impedance of VLWIR detectors, a high gain feedback amplifier was used to provide the inverting gain by a differential stage. By means of novel current mode background suppression, the integration time and the signal- to- noise ratio (SNR) of image data was increased when VLWIR FPAs run at high background environment. At the same time, better contrast and dynamic range was also achieved. The final chip was fabricated with HHNEC CZ6H 0.35μm 1P4M process technology. The test results show that the output dynamic range is over 2.0 V, the linearity could reach up to 99%, the readout frequency is more than 2.5 MHz, the RMS noise is less than 0.3 mV, and the power dissipation is less than 100 mW when the ROIC operates at the temperature of 50 K.