电子器件
電子器件
전자기건
JOURNAL OF ELECTRON DEVICES
2014年
2期
373-377
,共5页
电子电路设计%模2n+1乘法器%Booth/CSD编码%余数系统
電子電路設計%模2n+1乘法器%Booth/CSD編碼%餘數繫統
전자전로설계%모2n+1승법기%Booth/CSD편마%여수계통
electronic circuit design%module 2 n+1 multiplier%Booth/CSD encoding%RNS system
在余数系统的设计中,模加法器和模乘法器的设计处于核心地位,尤其是模乘法器的性能,是衡量余数系统系能的主要标志之一。文中先推导出Booth编码下的模2 n+1乘法器设计的算法,然后针对Booth编码模乘法器设计中译码电路复杂的问题,提出了一种基于Booth/CSD混合编码的模乘法器设计方法,基于Booth/CSD编码的模乘法器部分积的位宽相对传统的Booth编码乘法器而言,减少了50%;经试验证明,与传统的基-Booth编码的模乘法器相比这种混合编码的模乘法器的速度提高了5%,面积减少24.7%。
在餘數繫統的設計中,模加法器和模乘法器的設計處于覈心地位,尤其是模乘法器的性能,是衡量餘數繫統繫能的主要標誌之一。文中先推導齣Booth編碼下的模2 n+1乘法器設計的算法,然後針對Booth編碼模乘法器設計中譯碼電路複雜的問題,提齣瞭一種基于Booth/CSD混閤編碼的模乘法器設計方法,基于Booth/CSD編碼的模乘法器部分積的位寬相對傳統的Booth編碼乘法器而言,減少瞭50%;經試驗證明,與傳統的基-Booth編碼的模乘法器相比這種混閤編碼的模乘法器的速度提高瞭5%,麵積減少24.7%。
재여수계통적설계중,모가법기화모승법기적설계처우핵심지위,우기시모승법기적성능,시형량여수계통계능적주요표지지일。문중선추도출Booth편마하적모2 n+1승법기설계적산법,연후침대Booth편마모승법기설계중역마전로복잡적문제,제출료일충기우Booth/CSD혼합편마적모승법기설계방법,기우Booth/CSD편마적모승법기부분적적위관상대전통적Booth편마승법기이언,감소료50%;경시험증명,여전통적기-Booth편마적모승법기상비저충혼합편마적모승법기적속도제고료5%,면적감소24.7%。
In the design of RNS system the designs of,the modulo multiplier and adder are in a core position,espically the performance of the modulo mulitipliers,which is the main mark of a successfully RNS system. In this paper,we deduce the arithmetic used in the design of the Booth-based modulo multiplier first,and then in order to solve the problem of complex decoding circuit in design,we put forward a new method,in which we bring the efficient CSD enconding technology and radix-booth encoding techniques together, the partial product of Booth/CSD encoding module multiplier has a decrease of fifty percent compared with traditional Booth based module multiplier;the test results demonstrate that,in comparision with the traditional Booth based module multiplier the speed which we take Booth/CSD encoding method has an increase of five percent and the area has a decrease of twenty four point seven.