CAJ | 학술논문

Viterbi作为一种最大似然译码算法广泛应用在数字地面视频广播中,但由于其较高算法复杂程度,对实现高速低功耗时延小且逻辑结构简单的译码器带来了挑战。首先为了实现高速的Vit-erbi译码器,ACSU采用全并行结构,度量值的溢出控制采用取模归一化方法,并简化比较器。其次为了实现低功耗时延小且控制逻辑简单的Viterbi译码器,SMU采用改进的前向追溯结构,只用一组单口的RAM实现译码输出。该译码器在Xilinx Virtex6上实现并验证通过,并具有较好的译码性能。
Viterbi작위일충최대사연역마산법엄범응용재수자지면시빈엄파중,단유우기교고산법복잡정도,대실현고속저공모시연소차라집결구간단적역마기대래료도전。수선위료실현고속적Vit-erbi역마기,ACSU채용전병행결구,도량치적일출공제채용취모귀일화방법,병간화비교기。기차위료실현저공모시연소차공제라집간단적Viterbi역마기,SMU채용개진적전향추소결구,지용일조단구적RAM실현역마수출。해역마기재Xilinx Virtex6상실현병험증통과,병구유교호적역마성능。
Viterbi decoding is widely used in DVB-T communication system as a kind of maximum likeli-hood algorithm. For its high algorithm complexity, it brings many challenges to the realization of decoder with high speed,low power-consumption,little delay and simple logic structure. Firstly, in order to imple-ment high-speed Viterbi decoder, the structure is parallel in the ACS Unit, and the measurement of over-flow control is done with modulus normalization method,and meanwhile the comparator is simplified. Sec-ondly,in order to implement low power-consumption Viterbi decoder with simple control logic, SMU a-dopts the improved trace forward architecture and only a single RAM is used for decoding output. The de-coder is simulated and tested on Xilinx Virtex6 FPGA development board, and has good performance.