红外与激光工程
紅外與激光工程
홍외여격광공정
INFRARED AND LASER ENGINEERING
2014年
9期
2798-2804
,共7页
陈国强%张君玲%王攀%周杰%高磊%丁瑞军
陳國彊%張君玲%王攀%週傑%高磊%丁瑞軍
진국강%장군령%왕반%주걸%고뢰%정서군
碲镉汞e-APD%读出电路%主被动双模式成像%sigma-delta ADC%制冷型红外焦平面
碲鎘汞e-APD%讀齣電路%主被動雙模式成像%sigma-delta ADC%製冷型紅外焦平麵
제력홍e-APD%독출전로%주피동쌍모식성상%sigma-delta ADC%제랭형홍외초평면
HgCdTe e-APD%ROIC%passive/active imaging%sigma-delta ADC%cooled infrared FPA
HgCdTe e-APD工作于线性模式,通过内雪崩倍增效应将一个微弱的信号放大多个数量级。介绍了一个具有列共用ADC制冷型(77 K)数字化混成式HgCdTe e-APD FPA读出电路,可以应用于门控3D-LARDAR成像,有主被动双模式成像功能。 Sigma-delta转换器比较适合于中规模128×128焦平面列共用ADC。调制器采用2-1 MASH单比特结构,开关电容电路实现,数字抽取滤波器采用CIC级联梳状滤波器。采用GLOBALFOUNDRIES 0.35μm CMOS工艺,中心距100μm。设计了量化噪声抵消逻辑消除第一级调制器量化噪声,采用数字电路实现。CIC抽取滤波器的每一级寄存器长度以方差为指标截尾,以降低硬件消耗。并且数字抽取滤波器工作电压降低到1.5 V,可以进一步降低功耗。仿真显示sigma-delta转换器精度大于13 bit,功耗小于2.4 mW,转换速率7.7 k Samples/s。
HgCdTe e-APD工作于線性模式,通過內雪崩倍增效應將一箇微弱的信號放大多箇數量級。介紹瞭一箇具有列共用ADC製冷型(77 K)數字化混成式HgCdTe e-APD FPA讀齣電路,可以應用于門控3D-LARDAR成像,有主被動雙模式成像功能。 Sigma-delta轉換器比較適閤于中規模128×128焦平麵列共用ADC。調製器採用2-1 MASH單比特結構,開關電容電路實現,數字抽取濾波器採用CIC級聯梳狀濾波器。採用GLOBALFOUNDRIES 0.35μm CMOS工藝,中心距100μm。設計瞭量化譟聲牴消邏輯消除第一級調製器量化譟聲,採用數字電路實現。CIC抽取濾波器的每一級寄存器長度以方差為指標截尾,以降低硬件消耗。併且數字抽取濾波器工作電壓降低到1.5 V,可以進一步降低功耗。倣真顯示sigma-delta轉換器精度大于13 bit,功耗小于2.4 mW,轉換速率7.7 k Samples/s。
HgCdTe e-APD공작우선성모식,통과내설붕배증효응장일개미약적신호방대다개수량급。개소료일개구유렬공용ADC제랭형(77 K)수자화혼성식HgCdTe e-APD FPA독출전로,가이응용우문공3D-LARDAR성상,유주피동쌍모식성상공능。 Sigma-delta전환기비교괄합우중규모128×128초평면렬공용ADC。조제기채용2-1 MASH단비특결구,개관전용전로실현,수자추취려파기채용CIC급련소상려파기。채용GLOBALFOUNDRIES 0.35μm CMOS공예,중심거100μm。설계료양화조성저소라집소제제일급조제기양화조성,채용수자전로실현。CIC추취려파기적매일급기존기장도이방차위지표절미,이강저경건소모。병차수자추취려파기공작전압강저도1.5 V,가이진일보강저공모。방진현시sigma-delta전환기정도대우13 bit,공모소우2.4 mW,전환속솔7.7 k Samples/s。
HgCdTe electron injection avalanche photodiodes(e-APDs) work in linear mode. A weak optical current signal is amplified orders of magnitude due to the internal avalanche mechanism. The design of digital ROIC with a column-shared ADC for cooled (77 K) hybrid e-APDs FPA was presented in this paper. Sigma-delta conversion was a promising solution for high-performance and medium size FPA as 128 ×128. A multistage noise shaping (MASH) 2-1 single bit architecture sigma-delta ADC with switched-capacitor circuits was designed for column-shared ADC. A cascaded integrator-comb (CIC) filter was designed as the digital decimator filter. The circuit was implemented in the GLOBALFOUNDRIES 0.35μm CMOS process on the basis of a 100μm pixel pitch. A quantization noise subtraction circuit in modulator was designed to subtract the quantization noise of first-stage modulator. The register word length of the filter in each stage was carefully dimensioned in order to minimize the required hardware. Furthermore, the digital filters operate with a reduced supply voltage to 1.5 V. Simulation results showed that the sigma-delta conversion achieved the resolution higher than 13 bits and 2.4 mW power consumption per ADC at 7.7 k Samples/s rate.