CAJ | 학술논문

过硅通孔技术，提供了高密度、低延时和低功耗的垂直互连，芯片在三维方向堆叠的密度大、互连线短，从而使三维堆叠芯片成为可能。文章介绍了基于TSVs的三维堆叠芯片新的测试流程、TSVs绑定前测试的挑战和TSVs绑定后的可靠性与测试挑战，包括KGD与KGD晶圆级测试和老化、DFT 技术、绑定前可测性、测试经济性、TSVs绑定后的可靠性和测试问题，以及三维集成独有的问题，并介绍了这一领域的早期研究成果。
과규통공기술，제공료고밀도、저연시화저공모적수직호련，심편재삼유방향퇴첩적밀도대、호련선단，종이사삼유퇴첩심편성위가능。문장개소료기우TSVs적삼유퇴첩심편신적측시류정、TSVs방정전측시적도전화TSVs방정후적가고성여측시도전，포괄KGD여KGD정원급측시화노화、DFT 기술、방정전가측성、측시경제성、TSVs방정후적가고성화측시문제，이급삼유집성독유적문제，병개소료저일영역적조기연구성과。
Through-silicon vias(TSVs) technology provides high-density ,low-latency and low-power vertical interconnects through a thinned-down wafer substrate ,thereby enabling the creation of three-dimensional stacked ICs(3D-SICs) .The new 3D stacked chips test procedure based on TSVs ,the challenge of pre-bond test and the reliability and test challenge of TSVs post-bond are described ,including KGD and KGD wafer-level test and burn-in ,design for testability (DFT ) skill ,pre-bond testability ,test economy ,reliability and test problem of TSVs post-bond and problems that are unique to 3D integration .Then the early research re-sults in this area are summarized .