电子与信息学报
電子與信息學報
전자여신식학보
JOURNAL OF ELECTRONICS & INFORMATION TECHNOLOGY
2014年
5期
1258-1265
,共8页
杜世民%夏银水%储著飞%黄诚%杨润萍
杜世民%夏銀水%儲著飛%黃誠%楊潤萍
두세민%하은수%저저비%황성%양윤평
布图规划%固定边框%后布图优化%删除后插入算子%形状曲线相加
佈圖規劃%固定邊框%後佈圖優化%刪除後插入算子%形狀麯線相加
포도규화%고정변광%후포도우화%산제후삽입산자%형상곡선상가
Floorplanning%Fixed-outline%Post-floorplanning optimization%Insertion After Delete (IAD) operator%Shape curve adding
该文提出一种稳定的面向软模块的固定边框布图规划算法。该算法基于正则波兰表达式(Normalized Polish Expression, NPE)表示,提出一种基于形状曲线相加和插值技术的计算 NPE 最优布图的方法,并运用模拟退火(Simulation Annealing, SA)算法搜索最优解。为了求得满足固定边框的布图解,提出一种基于删除后插入(Insertion After Delete, IAD)算子的后布图优化方法。对8个GSRC和MCNC电路的实验结果表明,所提出算法在1%空白面积率的边框约束下的布图成功率接近100%,在总线长上较已有文献有较大改进,且在求解速度上较同类基于SA的算法有较大优势。
該文提齣一種穩定的麵嚮軟模塊的固定邊框佈圖規劃算法。該算法基于正則波蘭錶達式(Normalized Polish Expression, NPE)錶示,提齣一種基于形狀麯線相加和插值技術的計算 NPE 最優佈圖的方法,併運用模擬退火(Simulation Annealing, SA)算法搜索最優解。為瞭求得滿足固定邊框的佈圖解,提齣一種基于刪除後插入(Insertion After Delete, IAD)算子的後佈圖優化方法。對8箇GSRC和MCNC電路的實驗結果錶明,所提齣算法在1%空白麵積率的邊框約束下的佈圖成功率接近100%,在總線長上較已有文獻有較大改進,且在求解速度上較同類基于SA的算法有較大優勢。
해문제출일충은정적면향연모괴적고정변광포도규화산법。해산법기우정칙파란표체식(Normalized Polish Expression, NPE)표시,제출일충기우형상곡선상가화삽치기술적계산 NPE 최우포도적방법,병운용모의퇴화(Simulation Annealing, SA)산법수색최우해。위료구득만족고정변광적포도해,제출일충기우산제후삽입(Insertion After Delete, IAD)산자적후포도우화방법。대8개GSRC화MCNC전로적실험결과표명,소제출산법재1%공백면적솔적변광약속하적포도성공솔접근100%,재총선장상교이유문헌유교대개진,차재구해속도상교동류기우SA적산법유교대우세。
A stable Fixed-Outline Floorplanning (FOF) algorithm for soft module is proposed in this paper. It takes the Normalized Polish Expression (NPE) as a floorplan solution, using the shape curve adding algorithm and the interpolation technique to compute the best floorplan of a NPE. The Simulated Annealing (SA) algorithm is used to search the solution space. A post-floorplanning optimization method based on the new Insertion After Delete (IAD) operator is adopted to optimize those SA floorplan solutions which fail to meet the fixed-outline constraints. The experimental results on eight GSRC and MCNC benchmarks show that the proposed algorithm can not only achieve a nearly 100%floorplanning success rate under fixed-outline constraints with 1%white space but can also obtain better total wirelength than previous works. Besides, the proposed algortihtm has a greater advantage in the runtime over the similar SA-based algorithms.