CAJ | 학술논문

高精度、高性能浮点运算部件是高性能微处理器设计的重要部分。通过对传统双精度浮点乘加运算算法的研究，结合四倍精度浮点数据格式特点，设计并实现一种高性能的四倍精度浮点乘加器(QPFMA)，该乘加器支持多种浮点运算，运算延迟为7拍，全流水结构。采用双路加法器改进算法结构，优化头零预测和规格化移位逻辑，减小运算延迟和硬件开销。通过参数化设计验证方法，实现高效的正确性验证。逻辑综合结果表明，基于65 nm 工艺，该 QPFMA 频率可达1.2 GHz，比现有的 QPFMA 设计运算延迟减少3拍，频率提高约11.63%。
고정도、고성능부점운산부건시고성능미처리기설계적중요부분。통과대전통쌍정도부점승가운산산법적연구，결합사배정도부점수거격식특점，설계병실현일충고성능적사배정도부점승가기(QPFMA)，해승가기지지다충부점운산，운산연지위7박，전류수결구。채용쌍로가법기개진산법결구，우화두령예측화규격화이위라집，감소운산연지화경건개소。통과삼수화설계험증방법，실현고효적정학성험증。라집종합결과표명，기우65 nm 공예，해 QPFMA 빈솔가체1.2 GHz，비현유적 QPFMA 설계운산연지감소3박，빈솔제고약11.63%。
High precision and high performance floating-point unit is an important research object of high performance microprocessor design. According to the characteristic of Quadruple Precision(QP) floating-point data format and research on double precision floating-point multiplier accumulator algorithms, a high performance Quadruple Precision Floating-point Multiplier Accumulator(QPFMA) is designed and realized, which supports multiple floating-point arithmetic with a 7 cycles pipeline. By adopting dual path adder and improving on algorithm architecture, optimizing leading-zero-anticipation and normalization shifter logic, the latency and hardware area is decreased. And by making use of parameterized design and verification methodology, the correction of the QPFMA is verified efficiently. Based on 65 nm technology, as the synthesis results show that the QPFMA can work at 1.2 GHz, with the latency decreased by 3 cycles and the frequency increased by about 11.63% compared with current QPFMA design.