CAJ | 학술논문

针对高性能音频 D 类功放系统，基于现场可编程门阵列（field programmable gate array，FPGA）设计，实现了一个双声道均匀脉冲宽度调制（uniform pulse width modulation，UPWM）型 D 类功放控制器。该控制器使用由相同子滤波器抽头级联构成的半带滤波器并时分复用乘法器，以降低可配置插值滤波器的硬件资源消耗，利用 sigma-delta 调制器的高开环增益，通过构造一个基于查找表的误差校正模块，以较小的硬件代价来预校正控制器使用 UPWM 技术在信号带宽内所带来的非线性失真。测试结果表明该控制器输出信噪比可达114 dB，互调失真仅为-97 dB。
침대고성능음빈 D 류공방계통，기우현장가편정문진렬（field programmable gate array，FPGA）설계，실현료일개쌍성도균균맥충관도조제（uniform pulse width modulation，UPWM）형 D 류공방공제기。해공제기사용유상동자려파기추두급련구성적반대려파기병시분복용승법기，이강저가배치삽치려파기적경건자원소모，이용 sigma-delta 조제기적고개배증익，통과구조일개기우사조표적오차교정모괴，이교소적경건대개래예교정공제기사용 UPWM 기술재신호대관내소대래적비선성실진。측시결과표명해공제기수출신조비가체114 dB，호조실진부위-97 dB。
Based on the field programmable gate array (FPGA),a 2-channel uniform pulse width modula-tion (UPWM)controller for high performance class D audio power amplifier systems is designed and implemen-ted.To reduce the consumption of hardware resources,half-band filters,designed as a tapped cascaded inter-connection of identical sub-filters,and time division multiplexing for multiplier are employed in the configurable interpolation filter.A look-up table error correction module with low hardware requirements,taking advan-tage of the high open loop gain of the sigma-delta modulator,is implemented to pre-correct the UPWM non-linear distortion in baseband.The test results indicate that the controller achieves 114 dB signal-to-noise ratio and -97 dB inter-modulation distortion.