CAJ | 학술논문

为了解决无线通信系统结构复杂、硬件占用大的问题,设计了一种优化的流水线型 FFT/IFFT处理器。该 FFT处理器专为IEEE802.11n协议中SISO-OFDM系统设计,根据SISO-OFDM需完成64点、128点快速傅里叶变换(FFT)的特点,FFT处理器选择基2、基4混合算法,单路延迟反馈结构。硬件实现中,采用优化的蝶形运算单元,精简了旋转因子的存储,并设计了动态存取的输出寄存器等,输入输出位宽为10 bit时,在UMC 0.11μm CMOS工艺下将硬件描述优化成逻辑门阵列,面积约为0.3 mm2。与传统的存储器结构 FFT相比,大大减少了硬件开销和芯片面积及电路功耗。
위료해결무선통신계통결구복잡、경건점용대적문제,설계료일충우화적류수선형 FFT/IFFT처리기。해 FFT처리기전위IEEE802.11n협의중SISO-OFDM계통설계,근거SISO-OFDM수완성64점、128점쾌속부리협변환(FFT)적특점,FFT처리기선택기2、기4혼합산법,단로연지반궤결구。경건실현중,채용우화적접형운산단원,정간료선전인자적존저,병설계료동태존취적수출기존기등,수입수출위관위10 bit시,재UMC 0.11μm CMOS공예하장경건묘술우화성라집문진렬,면적약위0.3 mm2。여전통적존저기결구 FFT상비,대대감소료경건개소화심편면적급전로공모。
In order to simplify the complicity of the wireless communication system,a kind of FFT/IFFT processor is de-signed based on the SISO-OFDM system in IEEE 802.11n.Because the SISO-OFDM system needs 64 and 128 points fast Fourier transform,the FFT processor employs radix-4/2 mixed algorithm and single-path delay feedback architecture.The optimized butterfly unit is designed in the hardware.The simplified storage of twiddle factors and an optimized output RAM are also used to minimize the chip area.The 10 bit processor is designed in UMC 110 nm CMOS process,the chip area is a-bout 0.3 mm2 .Compared to the traditional memory based on FFT,the hardware cost and the power consumption are de-creased largely.