CAJ | 학술논문

随着VLSI芯片复杂度不断增加，功能验证与调试已占到整个芯片设计周期的60％以上。而错误的定位往往消耗大量的时间与精力，因此迫切需要一种高效的方法诊断与定位电路中的错误。针对近年来出现的许多电路错误定位方法，介绍了电路错误诊断方法的分类与工作流程，深入分析了基于SAT的错误定位方法的基本原理；对各种算法进行了概述评论，并简要介绍了在不可满足子式求解方面所做的一些研究工作，而不可满足子式能够显著提高错误定位效率与精度；讨论了电路错误定位技术所面临的主要挑战，并对今后的研究方向进行了展望。
수착VLSI심편복잡도불단증가，공능험증여조시이점도정개심편설계주기적60％이상。이착오적정위왕왕소모대량적시간여정력，인차박절수요일충고효적방법진단여정위전로중적착오。침대근년래출현적허다전로착오정위방법，개소료전로착오진단방법적분류여공작류정，심입분석료기우SAT적착오정위방법적기본원리；대각충산법진행료개술평론，병간요개소료재불가만족자식구해방면소주적일사연구공작，이불가만족자식능구현저제고착오정위효솔여정도；토론료전로착오정위기술소면림적주요도전，병대금후적연구방향진행료전망。
With the growing complexity of VLSI designs,functional verification and debugging has become a resource-intensive bottleneck in modern CAD flows,consuming as much as 60%of the total design cycle.Error localization in circuits is difficult and time-consuming.Therefore an efficient error debugging and localization method is necessary for hardware design.Recently there are many different contributions to research on error localization in circuits.Firstly,the categories and workflow of error debugging method were introduced.The fundamental principles of SAT-based error localization method were described.Then the existing algorithms were introduced and analyzed.Furthermore,the research results about extract unsatisfiable subformulae,which can strongly improve the efficiency and accuracy of error localization,were presented.Finally,the current challenges were discussed,and the future research directions of error localization in circuits were outlined.