计算机工程
計算機工程
계산궤공정
COMPUTER ENGINEERING
2014年
3期
306-309
,共4页
徐太龙%鲁世斌%代广珍%孟坚%陈军宁
徐太龍%魯世斌%代廣珍%孟堅%陳軍寧
서태룡%로세빈%대엄진%맹견%진군저
可测试性设计%低功耗%系统芯片%内建自测试%电源关断%多电源多电压%扫描链
可測試性設計%低功耗%繫統芯片%內建自測試%電源關斷%多電源多電壓%掃描鏈
가측시성설계%저공모%계통심편%내건자측시%전원관단%다전원다전압%소묘련
testability design%low power consumption%System-on-chip(SoC)%built-in-self-test%Power Shut-off(PSO)%Multi-supply Multi-voltage(MSMV)%scan chain
低功耗技术，如多电源多电压和电源关断等的应用，给现代超大规模系统芯片可测试性设计带来诸多问题。为此，采用工业界认可的电子设计自动化工具和常用的测试方法，构建实现可测试性设计的高效平台。基于该平台，提出一种包括扫描链设计、嵌入式存储器内建自测试和边界扫描设计的可测性设计实现方案。实验结果表明，该方案能高效、方便和准确地完成低功耗系统芯片的可测性设计，并成功地在自动测试仪上完成各种测试，组合逻辑和时序逻辑的扫描链测试覆盖率为98.2%。
低功耗技術，如多電源多電壓和電源關斷等的應用，給現代超大規模繫統芯片可測試性設計帶來諸多問題。為此，採用工業界認可的電子設計自動化工具和常用的測試方法，構建實現可測試性設計的高效平檯。基于該平檯，提齣一種包括掃描鏈設計、嵌入式存儲器內建自測試和邊界掃描設計的可測性設計實現方案。實驗結果錶明，該方案能高效、方便和準確地完成低功耗繫統芯片的可測性設計，併成功地在自動測試儀上完成各種測試，組閤邏輯和時序邏輯的掃描鏈測試覆蓋率為98.2%。
저공모기술，여다전원다전압화전원관단등적응용，급현대초대규모계통심편가측시성설계대래제다문제。위차，채용공업계인가적전자설계자동화공구화상용적측시방법，구건실현가측시성설계적고효평태。기우해평태，제출일충포괄소묘련설계、감입식존저기내건자측시화변계소묘설계적가측성설계실현방안。실험결과표명，해방안능고효、방편화준학지완성저공모계통심편적가측성설계，병성공지재자동측시의상완성각충측시，조합라집화시서라집적소묘련측시복개솔위98.2%。
The low power design technologies such as Multi-supply Multi-voltage(MSMV) and Power Shut-off(PSO), present many challenges for the testability design of modern very large scale integration System-on-chip(SoC). Based on the efficient implementation platform constructed by using the industrial electronic design automation tools and the widely used testability methods, a testability design scheme that includes the scan chain, memory built-in-self-test and boundary scan is proposed. Experimental results show that the scheme can efficiently, conveniently and accurately complete the testability design of low power consumption SoC, and works correctly in automation test equipment. The test coverage of combinational and sequential logic scan chains is 98.2%.
