哈尔滨工程大学学报
哈爾濱工程大學學報
합이빈공정대학학보
JOURNAL OF HARBIN ENGINEERING UNIVERSITY
2014年
3期
368-372
,共5页
薛金勇%黑勇%陈黎明
薛金勇%黑勇%陳黎明
설금용%흑용%진려명
快速高效无损图像压缩系统%Golomb-Rice编码%吞吐量%超大规模集成电路%贝尔图像%低功耗
快速高效無損圖像壓縮繫統%Golomb-Rice編碼%吞吐量%超大規模集成電路%貝爾圖像%低功耗
쾌속고효무손도상압축계통%Golomb-Rice편마%탄토량%초대규모집성전로%패이도상%저공모
FELICS%Golomb-Rice code%throughput%VLSI%Bayer image%low power
针对快速高效无损图像压缩系统( FELICS)中,Golomb-Rice编码k参数选取增加系统复杂度和限制系统吞吐量的问题,依据基于上下文的图像压缩理论,采用JPEG-LS中的序列参数估计方法,研究了限长Golomb-Rice编码。给出了面向超大规模集成电路( VLSI)实现的低功耗快速高效无损图像压缩系统。 VLSI-oriented FELICS 简化了k参数的选取,提高了系统的吞吐率;针对贝尔图像格式的算法扩展提高了FELICS算法对Bayer图像的压缩效果。在SMIC 0.13μm工艺条件下,基于该方法完成了面向低功耗胃窥镜的VLSI 设计。当系统工作在25 MHz,图像数据时钟为24 MHz时,编码每帧图像的功耗仅为11.15μW,VGA图像的吞吐率可以达到60 f/s。
針對快速高效無損圖像壓縮繫統( FELICS)中,Golomb-Rice編碼k參數選取增加繫統複雜度和限製繫統吞吐量的問題,依據基于上下文的圖像壓縮理論,採用JPEG-LS中的序列參數估計方法,研究瞭限長Golomb-Rice編碼。給齣瞭麵嚮超大規模集成電路( VLSI)實現的低功耗快速高效無損圖像壓縮繫統。 VLSI-oriented FELICS 簡化瞭k參數的選取,提高瞭繫統的吞吐率;針對貝爾圖像格式的算法擴展提高瞭FELICS算法對Bayer圖像的壓縮效果。在SMIC 0.13μm工藝條件下,基于該方法完成瞭麵嚮低功耗胃窺鏡的VLSI 設計。噹繫統工作在25 MHz,圖像數據時鐘為24 MHz時,編碼每幀圖像的功耗僅為11.15μW,VGA圖像的吞吐率可以達到60 f/s。
침대쾌속고효무손도상압축계통( FELICS)중,Golomb-Rice편마k삼수선취증가계통복잡도화한제계통탄토량적문제,의거기우상하문적도상압축이론,채용JPEG-LS중적서렬삼수고계방법,연구료한장Golomb-Rice편마。급출료면향초대규모집성전로( VLSI)실현적저공모쾌속고효무손도상압축계통。 VLSI-oriented FELICS 간화료k삼수적선취,제고료계통적탄토솔;침대패이도상격식적산법확전제고료FELICS산법대Bayer도상적압축효과。재SMIC 0.13μm공예조건하,기우해방법완성료면향저공모위규경적VLSI 설계。당계통공작재25 MHz,도상수거시종위24 MHz시,편마매정도상적공모부위11.15μW,VGA도상적탄토솔가이체도60 f/s。
The Golomb-Rice code of the fast and efficient lossless image compression system ( FELICS) requires es-timation of the coding parameter value k, which increases the system complexity and limits the throughput of the system.This research into the limited-length Golomb-Rice code adopting sequential parameter estimation of JPEG-LS was made based on the context model of the image compression theory .The very large scale integration ( VLSI)-oriented low power FELICS algorithm was proposed .The VLSI-oriented low power FELICS algorithm simplified the selection of the coding parameter and improved the throughput of the system .The VLSI-oriented FELICS with Bayer expansion improved the compression ratio of the Bayer images .The VLSI design based on the proposed algorithm was implemented under the condition of the SMIC ( Semiconductor Manufacturing International Corporation ) 0.13 μm process.When the system works at 25 MHz clock frequency with a 24 MHz pixel clock frequency in VGA resolution, the power dissipation per frame is only 11.15μW, and the throughput of the system is up to 60 frames per second .