电子设计工程
電子設計工程
전자설계공정
ELECTRONIC DESIGN ENGINEERING
2012年
11期
85-88
,共4页
二叉树%时序电路%测试序列%状态验证%故障检测
二扠樹%時序電路%測試序列%狀態驗證%故障檢測
이차수%시서전로%측시서렬%상태험증%고장검측
binary tree%time sequence circuit%test sequence%status verification%fault detection
为了实现时序电路状态验证和故障检测,需要事先设计一个输入测试序列。基于二叉树节点和树枝的特性,建立时序电路状态二又树,按照电路二叉树节点(状态)与树枝(输入)的层次逻辑关系,可以直观和便捷地设计出时序电路测试序列。用测试序列激励待测电路,可以验证电路是否具有全部预定状态,是否能够实现预定状态转换。
為瞭實現時序電路狀態驗證和故障檢測,需要事先設計一箇輸入測試序列。基于二扠樹節點和樹枝的特性,建立時序電路狀態二又樹,按照電路二扠樹節點(狀態)與樹枝(輸入)的層次邏輯關繫,可以直觀和便捷地設計齣時序電路測試序列。用測試序列激勵待測電路,可以驗證電路是否具有全部預定狀態,是否能夠實現預定狀態轉換。
위료실현시서전로상태험증화고장검측,수요사선설계일개수입측시서렬。기우이차수절점화수지적특성,건립시서전로상태이우수,안조전로이차수절점(상태)여수지(수입)적층차라집관계,가이직관화편첩지설계출시서전로측시서렬。용측시서렬격려대측전로,가이험증전로시부구유전부예정상태,시부능구실현예정상태전환。
For the purpose of time sequential circuit status verification and fault detection, a pre-determined test sequence will be input to stimulate the circuit. Based on the properties of circuit binary tree node and branch, time sequence circuit binary tree can be established and then directly and precisely design the test sequence according to the circuit binary tree's node (status) and branch (input) layer and logical relationship. Corresponding output is the analysis to test whether the circuit shows the expected status, and whether it can achieve the expected status transformation.