CAJ | 학술논문

最近研究表明，静态存储器（SRAM）功耗是整个芯片功耗的重要组成部分，功耗问题在SRAM单元设计中成为一个日益重要的问题。提出了一种新的纳米级的高稳定性和低功耗应用技术，采用该技术的SRAM单元采用分开的读写机制。65nmCMOS工艺的仿真结果表明，此新型的SRAM单元结构在保证正确的读写操作下，在写0操作时功耗比传统的SRAM单元降低22．45％。同时，此新型SRAM在空闲模式下利用漏电流和正反馈存值，极大地提高了SRAM单元的稳定性，改善了纳米尺度下SRAM单元的功耗问题。
최근연구표명，정태존저기（SRAM）공모시정개심편공모적중요조성부분，공모문제재SRAM단원설계중성위일개일익중요적문제。제출료일충신적납미급적고은정성화저공모응용기술，채용해기술적SRAM단원채용분개적독사궤제。65nmCMOS공예적방진결과표명，차신형적SRAM단원결구재보증정학적독사조작하，재사0조작시공모비전통적SRAM단원강저22．45％。동시，차신형SRAM재공한모식하이용루전류화정반궤존치，겁대지제고료SRAM단원적은정성，개선료납미척도하SRAM단원적공모문제。
Power consumption is becoming a pressing issue in SRAM cell design. Recent research shows that SRAM power contributes a key part of the whole chip power consumption. In this paper, we present a new 6T-SRAM cell structure for nano-scale technology with stability of low power application by using separate write and read operation. Simulation results with standard 65nm CMOS technology show the correct operation, the speed is closed to the traditional 6T cell, power consumption reduces about 22.45% during write 0. In particular, this structure maintains its data with leakage current and positive feedback in idle mode which can greatly improve the power consumption of the nano-scale SRAM.